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Day One |
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Company |
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Monday, April 19 |
Session |
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University |
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7:00 am - 5:00
pm |
Registration Open All Day |
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8:00 am - 8:15
am |
Welcome and Opening Remarks, Technology/Market Trends, Farhad Mafie,
President and CEO |
Savant |
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8:15 am - 10:15
am |
ASIC/SoC/Foundry for 90nm and Sub-90nm |
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ASIC/SoC 90nm and Beyond.
Ronnie V. Vasishta, Vice President of Technology Marketing & CoreWare
Engineering |
LSI Logic |
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Partnering with Foundries to
Bring Your SoC Design to Market. Walter Ng, Senior Director, Design
Solutions
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Chartered Semiconductor |
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An initiative to reduce
leakage currents/die sizes in advanced technology ASICs without sacrificing
performance. Sunil Baliga, VP Marketing and Business Development, |
Kawasaki Microelectronics |
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An Emerging New Business Model for the Post-90nm
Semiconductor Industry. Bradley Howe, Vice President, IC Design
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Altera |
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10:15 am - 10:30 am
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Morning Break -- Coffee Hosted by @HDL
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10:30 am - 12:00 am |
SoC
Design Challenges |
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SoC Tradeoffs in a
High-Voltage Isolation Environment: Based on Experiences with
Communication ICs such as Analog Modems.
Surinder Rai,
Director, Computing Connectivity Division |
Agere System |
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Low-Power SoC Design Using Voltage Islands
and Adaptive Voltage Scaling. Gordon Mortensen, Engineering Manager -
Advanced Technology |
National Semiconductor |
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Integration of Third-Party Intellectual Property into an SoC
Design. Michael Ou, Principal Design Engineer |
Palmchip |
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12:00 am - 1:00 pm |
Lunch |
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1:00 pm - 1:30 pm |
Keynote Speech:
Engineering the Education:
Challenges in
Preparing Tomorrow's SoC Technical Workforce. Dr.
Raman Menon Unnikrishnan - Dean, College of Engineering and Computer Science |
CSU, Fullerton |
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1:30 pm - 3:30 pm |
Configurable CPUs and
DSPs for SoC Platform Design |
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ARC’s turnkey embedded solutions for SoC Design: processor
core, real-time operating system, development tools, and peripheral
hardware and software IP.
David Fritz, Vice President
of Marketing for SoC
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ARC International |
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Designing with Configurable Processors
Instead of RTL. Steve Leibson, Technology Evangelist |
Tensilica |
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Meeting
the SoC needs of demanding next-generation consumer applications.
Ralph Weir, Director of
Technical Marketing |
Elixent |
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Reconfigurable Digital Signal Processors (RDSPs). Dr.
Nader Bagherzadeh |
UC Irvine |
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3:30 pm - 3:50 pm |
Afternoon Break |
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3:50 pm - 5:30 pm
Panel |
Panel: Configurable CPUs/DSPs for SoC Platform Design
Moderator: Ron Wilson, Editor, EE Times.
Panelists:
1)
David Fritz, Vice President of
Marketing for SoC,
ARC International
2)
Steve Leibson, Technology Evangelist, Tensilica
3) Dr.
Nader Bagherzadeh,
Professor, Department of Electrical and Computer Engineering, UCI
4)
Ralph Weir, Director of Technical Marketing,
Elixent
5)
Chinh Le, CEO and CTO, LeWiz Communications
Inc.
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5:30 pm - 8:00 pm |
Exhibition Room Open |
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Day Two |
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Company |
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Tuesday, April 20 |
Session |
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University |
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7:00 am - 5:00 pm |
Registration Open |
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7:45 am - 8:00 am |
The
Next Generation of System-on-Chip Devices. Jauher Zaidi, CEO of
Palmchip Corporation and Member, Savant Board of Advisors |
Savant |
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8:00 am - 10:00 am |
SoC Design Using
Programmable ICs & Structured ASIC |
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SoC Challenges and Opportunities for Programmable Devices at 90nm and Below.
Richard Terrill, Senior Manager, Higher Volume Solutions |
Xilinx |
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How to Achieve ROI in 90nm ASIC Development,
Phillip LoPresti,
Associate Vice President and General Manager of the Custom LSI Solutions
Strategic Business Unit |
NEC Electronics |
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SoC
Power Supply Management Using an Integrated Programmable Mixed Signal
Device. Shyam Chandra, Marketing Manager |
Lattice |
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Maximizing the Possible Benefits of Structured ASIC
Technology. Ganesh Narayanaswamy, Product Marketing Manager |
Altera |
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10:00 am - 10:15 am |
Morning Break -- Coffee Hosted By Toshiba
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10:15 am - 12:15 pm |
System-on-Chip Platform
Design |
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Implementing a System-on-Chip Platform Methodology in the Design Flow
Requires a New Way of Thinking. Jim Venable, Senior Vice President |
Palmchip |
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Implementing a System-on-Chip Platform for High-Performance Communications
Processors. Lakshmi Mandyam
PowerQUICC III Marketing
Manager |
Motorola |
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Redefining
SoC: From System- to Solution-on-Chip.
Shri Sundaram,
System Engineering Manager |
Toshiba |
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Accelerating Custom SoC Design Using
RapidChip Platform ASIC with System CoreWare IP.
Balraj
(Raj) Singh, Senior Marketing Manager, LSI Logic CoreWare Technology Group.
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LSI Logic |
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12:15 pm - 1:15 pm |
Lunch |
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1:15 pm - 1:45 pm |
Keynote Speech: New Realities Mandate Fundamental Changes in
Competitive Strategies. Derek Lidow, President and CEO |
iSuppli |
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1:45 pm - 2:15 pm |
SoC-Enabled Parallel Processing Platform
for IP Storage and Content Delivery Applications. JeanClaude Toma,
Vice President, Marketing and Business Development
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Xiran |
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2:15 pm - 4:15 pm |
EDA Tools and
Methodologies for
Nanometer
SoCs |
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Front-end Design for
Nanometer SoCs. Chi-Ping Hsu, Corporate VP – New Synthesis |
Cadence Design Systems
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Power Modeling Challenges for 90nm.
Robert Jones, Director, Strategic Marketing, Magma's Silicon
Correlation Division |
Magma SCD |
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EDA Tools for SoC High-Level
Design and Verification.
Dave Apte,
System Level Design Specialist |
Summit Design |
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Raising
SoC Design Productivity Though Systems That Support Effective Reuse. Pedro
Santos, Manager |
Synchronicity |
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4:15 pm - 4:30 pm |
Afternoon Break |
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4:30 pm - 6:00 pm
Panel |
Panel: EDA Tools for 90nm and Post-90nm
Moderator:
Dave Bursky,
Editor-at-Large,
Electronic Design
Magazine
Panelists:
1)
Steve Carlson,
Director, Cadence Synthesis
Team
2) Robert Jones,
Director, Strategic Marketing, Silicon Correlation Division,
Magma
3)
John A.
Ford, Vice President of Marketing,
Virtual Silicon
4) Dr. Wagdy, Professor of Electrical and
Computer Engineering, CSU Long Beach
5)
Dr.
Martine Simard-Normandin, President and CEO, MuAnalysis
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6:00 pm - 6:15 pm |
Closing Remarks |
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