SAVANT Thanks our Sponsors!
1st International System-on-Chip
Detailed Program Information for Monday, April 19, 2004*
8:00 - 8:15
Welcome and Opening Remarks, Technology/Market Trends, Farhad Mafie,
President and CEO
8:00 - 8:15
Mafie, President and CEO of Savant Company Inc.
Farhad Mafie, President and CEO of Savant Company Inc., has
over 20 years of experience in electronic and computer businesses and more
than 10 years of university-level teaching experience. Farhad is the
former Vice President of Business Development and Technical Sales
Engineering at Toshiba America Electronic Components, Inc. He has also
worked at Lucent Technologies, Toshiba Information Systems, Unisys, and MSI
Data in strategic marketing, and project engineering capacities for system
and chip design. Farhad has a Master of
Science and a Bachelor of Science degree in Electronic Engineering and
Computer Design from California State University, Fullerton.
combined business and academic experience has given Farhad a unique ability
to effectively communicate complex new technologies to business
professionals at all levels, as well as the ability to foresee emerging
leading-edge technologies. An avid bicyclist, Farhad is also an author
and a translator, and he writes articles for a variety of journals and
Web-based magazines on world affairs.
8:15 am - 10:15 am
ASIC/SoC/Foundry for 90nm and Sub-90nm
V. Vasishta, Vice President of Technology Marketing & CoreWare®
Engineering, LSI Logic Corporation
90nm and Beyond"
associated with complex SoC design seem to increase with every new
generation of technology. As these challenges mount, what we are really
faced with is the cost of managing or harnessing complexity. History has
shown that when faced with a challenge, a new approach to addressing the
challenge is developed. These new approaches, often called “disruptive
technologies,” once again enable a wider user base. As we move into the era
of multi-mega gate SoC design, it is obvious that the current alternatives
of FPGAs and ASSPs, while valuable in their own spaces, do not provide the
disruption required to bring complex SoC design to the masses at 130nm and
90nm. This is where Platform ASICs come in. They are gaining
acceptance and soon will be moving into the mainstream. But just what
is a Platform ASIC and how does it fit into the landscape of custom logic
is Vice President of Technology Marketing and CoreWare® Engineering for LSI
Logic Corporation. He oversees the companywide strategic technology
direction and the definition and development of LSI Logic’s technology
products, including silicon technologies, intellectual property cores,
design tools and methodologies, advanced packaging, embedded memory, and
I/Os. In addition, he has responsibility for direct marketing support
for customers, sales, vertical market groups, and design centers.
Vasishta’s responsibilities also include the marketing and engineering of
LSI Logic’s CoreWare® Engineering program, which includes CoreWare®
methodology, development, and field support engineering, as well as
interfaces with third-party IP providers.
Ng, Senior Director, Design Solutions, Chartered Semiconductor Manufacturing
"Partnering with Foundries
to Bring Your SoC Design to Market"
complexity, implementation cost, and time to fully functional silicon are
primary concerns in bringing today's SoC designs to market. Foundries must
provide support to their customers' design teams through silicon-proven
libraries and intellectual property, proven design flows, and extensive and
accurate device models to achieve high probability of first pass design
success, which addresses both cost and time. Partnering with your foundry of
choice becomes even more critical given the design challenges of 90
nanometer and beyond. Understanding where the foundry industry is heading
and how to maximize your foundry relationships figure prominently in
achieving system requirements.
Walter Ng is
responsible for driving and managing Chartered's business and marketing
relationships with third-party IP and EDA partners. Mr. Ng has been in
the electronic design and EDA industry for more than 13 years, holding a
variety of business development, sales, and marketing positions at Sequence
Design and Cadence. He also held various senior design and test engineering
positions in Raytheon's Equipment Development Labs in the area of
satellite communications. Mr. Ng holds a BSEE from the University of
Massachusetts, Amherst, and an MBA from the University of Massachusetts,
Baliga, VP Marketing and Business Development, Kawasaki Microelectronics
initiative to reduce leakage currents/die sizes in advanced technology
ASICs without sacrificing performance"
currents are one of the most vexing problems facing designers of advanced
technology ASICs. Kawasaki will share details of a new initiative,
launched in conjunction with its partners, that will reduce leakage
currents and die sizes, without sacrificing performance, in advanced
technology ASICs. An additional benefit of this initiative is the
reduction in NRE costs for making derivatives products from a platform
Baliga has more than 15 years of experience in marketing semiconductors,
primarily in the programmable logic and ASIC markets. He has a BSEE from
the University of Colorado and an MBA from Georgetown University. Sunil
was recently re-elected to a second term as chair of the Network
Processing Forum's marketing working group.
Howe, Vice President, IC Design, Altera Corporation
Emerging New Business Model for the Post-90-nm Semiconductor Industry"
As the semiconductor industry
migrates to 90-nm processing and beyond, it is rapidly becoming clear that a
new business model is going to be needed to ensure both continued innovation
and economic success. Rising processing and IC development costs,
coupled with dramatically increasing design complexities, are making it
critical for IC companies to work closely with their foundry and IP partners
to ensure the separate technologies each brings can be successfully
integrated to produce the devices the market requires. This paper will
discuss the factors driving the emergence of this evolving business model
and detail the challenges involved in its successful implementation, its
potential benefits, and the likely fate of those companies which fail to
make the transition.
Bradley Howe joined Altera
in 2002 and serves as Vice President of IC Design, responsible for the
development of Altera's silicon products. With 20 years of industry
experience, he has held a number of senior engineering and managerial
positions that include Vice President of Engineering at C-Cube Microsystems,
Clearwater Networks, and SandCraft. He holds a BS and an MS in
Computer and Electrical Engineering from Boston University.
10:15 am - 10:30 am
-- Coffee Hosted by @HDL
10:30 am - 12:00 am
Director, Computing Connectivity Division,
Tradeoffs in a High-Voltage Isolation Environment: Based on
Experiences with Communication ICs such as Analog Modems"
presentation will discuss how system-level partitioning decisions with
respect to silicon partitioning the SoC were made in real-life cases with
respect to communication ICs such as analog modems. The objective is
an attempt to evolve a set of criteria for each SoC situation by
establishing the basic fact that the optimum solution is very much dependent
on the overall business and technology constraints. This study will tradeoff
certain criteria of business success: R&D investment, revenue, margin
dollars, and time-to-market alongside key technology tradeoffs:
silicon partitioning, silicon costs, overall solution costs, power
dissipation, and performance. It will attempt to derive the decisions as to
how the analog modem product line took advantage of the process technology
roadmap. The reason for selecting the analog modem business in this case is
the familiarity of the author with this business during the last decade, in
addition to the fact that analog modems are typical of some of the very
issues that SoC-based product lines encounter in the real world. This
presentation objective is to establish a simple matrix/criteria which could
be easily applied to any other SoC product line.
Surinder Singh Rai is
Director of the Computing Connectivity Division of Agere Systems. Agere is a premier provider of
advanced integrated circuit solutions for wireless data, high-density
storage, and multiservice
networking applications. In this capacity since 2001, Surinder has
responsibility for the wired product line, which includes analog modems,
1394-based standard products, and USB-based standard products. These
responsibilities include the overall product portfolio and strategy
direction, P&L results, and customer relationships. Before assuming his current position, Surinder
was Marketing Director for Agere’s Analog Modem product line for four years,
with overall responsibility for product strategy, product design-in, and
customer support. Under Surinder’s guidance, Agere’s Analog Modem
business doubled in a four-year period. Prior to joining Agere, Surinder was
a marketing manager for AT&T Microelectronics, responsible for the PC
Graphics product line, with an emphasis on RAMDACs for PCs and workstations.
Surinder holds a patent titled “CMOS Output Buffer Providing High Drive
Current” (#4638187). Surinder received an MBA from the College of St.
Thomas in St. Paul, Minnesota; a Master’s degree in Electrical Engineering
from the State University of New York at Stony Brook; and a Bachelor’s
degree in Electrical Engineering from BITS in Pilani, India.
Mortensen, Engineering Manager - Advanced Technology, Portable Power Group,
"Low Power SoC Design Using Voltage Islands
and Adaptive Voltage Scaling"
of Adaptive Voltage Scaling (AVS) can greatly reduce power consumption and
improve energy efficiency in SoC designs. This discussion/paper will present
simulated and measured power savings with AVS and investigate voltage island
partitioning options for low power SoC design.
is an Engineering Manager in the Advanced Technology section of the Portable
Power Group at National Semiconductor. He has 21 years of experience in the
semiconductor industry in engineering management, as a design engineer, and
as a product engineer. Gordon's embedded systems experience includes 4-bit,
8-bit and 16-bit microcontroller products, x86 platform chipsets, and
Portable Power Management products.
Ou, Principal Design Engineer, Palmchip Corporation
"Integration of Third-Party Intellectual Property into an
presentation discusses the challenges of integration of third-party IP into
an SoC design from both an IP-user and an IP-supplier perspective. The
presentation focuses on issues encountered during the integration process,
including connecting the IP to the system, verification, and synthesis and
suggests strategies to deal with these issues for both IP users and IP
Michael Ou works
as a Principal Design Engineer at Palmchip Corporation, where he is
responsible for IP Development and Platform Technology. Prior to
Palmchip, he worked as an ASIC design engineer at Quantum, Adaptec, and
Amdahl Corporation. He received his BSEE from Princeton University and
MSEE from Stanford University.
112:00 am - 1:00 pm
1:00 pm - 1:30 pm
Dr. Raman Menon Unnikrishnan. Dean
of the College of Engineering and Computer Science, California State
"Engineering the Education:
Challenges in Preparing Tomorrow's SoC Technical Workforce"
No; it is not a mistake; it is
engineering the education. Engineering as a verb refers to the act of
finding solutions to complex problems. Educating tomorrow’s engineers is a
complex problem that requires innovative approaches and answers. The talk
begins with the recognition of the metamorphosis of engineering as a
discipline. It recognizes the changes that are taking place in the US
secondary education that influences the quality of the student body entering
universities. The educational planners must, however, take into
consideration the changing needs of industry that ranges from routine design
work to nanotechnology and System on a Chip look at engineering operations
as a global enterprise. The talk covers what is being done to address these
challenges as well as what we must be doing to meet the demands of the
Dr. Raman Menon Unnikrishnan
is Professor of Electrical Engineering and Dean of the College of
Engineering and Computer Science. He is active in teaching and research in
the areas of Control Systems, Power Electronics, and Signal Processing and
is an author of numerous research papers and presentations in these areas.
He has been a consultant to several industries and governmental agencies and
has been involved in technical and professional education for industries. He
is active nationally in the field of Engineering Education and Engineering
Accreditation. Prior to joining Cal State Fullerton, Dr. Unnikrishnan was on
the faculty of the Rochester Institute of Technology in Rochester, New York,
where he also served as Associate Dean for Graduate Studies and Research for
the College of Engineering from 1989 to 1991 and as the Head of the
Electrical Engineering Department from 1991 to 2001. He received his BS
degree from the University of Kerala, India, his MS from South Dakota State
University, and his Ph.D. degree from the University of Missouri, all in
electrical engineering. Dr. Unnikrishnan is a member of Eta Kappa Nu, Tau
Beta Pi, ASEE, and a Senior Member of IEEE.
1:30 pm - 3:30 pm
Configurable CPUs and
DSPs for SoC Platform Design
David Fritz, Vice President of
Marketing for SoC,
"ARC’s turnkey embedded solutions for SoC Design: processor
core, real-time operating system, development tools, and peripheral hardware
and software IP"
ARC’s solutions accelerate development
and optimize results minimize risk for customers developing a wide range
next-generation wireless, networking, industrial control, storage and
consumer electronics products. ARC introduced the
industry’s first user-customizable 32-bit RISC/DSP processor core and the
industry's first USB Hi-Speed On-The-Go IP. ARC’s turnkey embedded
solutions, combining the processor core with a real-time operating system,
development tools and peripheral hardware and software IP, enable developers
to optimize the design and performance of their applications. By providing
designers with a single source for all major embedded silicon and software
IP building blocks, ARC dramatically reduces their number of suppliers,
thereby reducing cost,
reducing risk and reducing
holds degrees in Mathematics and Computer Science from Manchester College
and began his career at Texas Instruments and DSC Communications. He was the
founder and president of Production Languages Corporation, a pioneer in
configurable processor technology, where he was awarded a US patent covering
fundamental processes related to configurable processors. Production
Languages Corporation was subsequently acquired by ZiLOG in 1999, and Mr.
Fritz became vice president of ZiLOG’s Advanced Cores R & D as well as vice
president of ZiLOG’s Development Systems Group. He currently serves as vice
President of Technical Marketing for ARC International.
Leibson, Technology Evangelist, Tensilica, Inc.
with Configurable Processors Instead of RTL"
microprocessor cores are the universal building blocks for SoC designs, but
they aren’t fast enough to solve many application problems. SoC designers
often resort to designing and verifying hardware accelerators to bridge the
performance gap, with a substantial loss in application flexibility. Rather
than designing RTL hardware blocks for performance-intensive tasks, it’s
much faster and more efficient to tailor application-specific processors to
perform on-chip tasks. These processors deliver the required hardware-level
performance with microprocessor flexibility. This session discusses how
application-specific processors provide a superior alternative to hard-wired
RTL for performance-intensive SOC tasks. It also discusses how multiple
processors can effectively be used in SOC design to meet schedule,
performance, and cost goals.
is the Technology Evangelist for Tensilica, Inc. He has formerly served as
the Vice President of Content and Editor in Chief of the Microprocessor
Report, Editor in Chief of EDN Magazine, and Founding Editor in Chief of
Embedded Developers Journal magazine. He has written hundreds of articles
that have appeared in several electronics industry trade magazines, and he
has won many industry awards for his writing. While at MDR, Leibson
developed and presented many microprocessor seminars and he organized and
served as MC for the Microprocessor and Embedded Processor Forums. He holds
a BSEE Cum Laude from Case Western Reserve University and worked as a design
engineer and engineering manager for leading-edge system-design companies
including Hewlett-Packard and Cadnetix before becoming a journalist.
Weir, Director of Technical Marketing, Elixent, Inc.
"Meeting the SoC needs of demanding next-generation consumer
consumer electronics industry is facing conflicting demands for increased
performance and functionality, increased battery life and shorter product
life cycles. In this presentation Elixent will describe these challenges in
a world dominated by billion-dollar wafer fab dynamics. We will then show
how Reconfigurable Algorithm Processing (RAP) technology can turn these
dynamics to the designer's advantage, aiding silicon designers in developing
SoCs that meet these tough requirements and that are not only viable, but
profitable. RAP is a programmable platform allows silicon-efficient
implementation of algorithms that are best implemented in hardware - for
example, multimedia & SDR processing. It does this in a programmable and
very low power manner, unlike traditional DSPs or RISCs - which
are typically too slow and carry significant overhead. It does this without
committing the algorithm before tape-out, as is the case with traditional
configurable CPUs. Instead, it is a complementary technology to
configurable CPUs, allowing them to remain relevant in the 90nm age and
Ralph joined Elixent in
March 2001 and has been instrumental in the marketing of reconfigurable
technology since then. Before joining Elixent, he was Sales & Marketing
Director of Hunt Engineering, a DSP systems specialist, which he joined
from Blue Wave Systems where he had been Director of Marketing. (Blue
Wave Systems was the world's largest DSP Systems supplier, formed from the
merger of Mizar and Loughborough Sound Images, and subsequently acquired
by Motorola Computer Group). Ralph has also held senior business
development and marketing positions at Texas Instruments and Motorola
Semiconductors. In both of these roles he had responsibility for DSP,
giving a career of some 17 years in the DSP industry. He is a graduate of
Strathclyde University in Scotland.
Signal Processors (RDSPs)"
growth and development of SoC technologies relies on the longer life cycle
of the new chips in wireless communication and media processing. The
current approach of integrating ASIC solutions is not economically
attractive for the new generation of SoC chips, because of the NRE expenses
(mask, engineering, validation, etc.) and the shorter life cycle of the
product. Therefore, reprogrammable technologies such as reconfigurable
highly parallel DSPs are the most cost effective approach that meets the
real-time performance and power requirements of the next generation SoCs and
can migrate across product generations meeting new standards and in-field
Bagherzadeh has been involved in research and development in the areas of
computer architecture, reconfigurable computing, VLSI chip design, and
computer graphics. For almost ten years ago, he was the first researcher
working on the VLSI design of a Very Long Instruction Word (VLIW) processor.
Since then, he has been working on multithreaded superscalars and their
application to signal processing and general purpose computing. His
current project at UC, Irvine is concerned with the design of coarse grain
reconfigurable pixel processors for video applications. The proposed
architecture, called MorphoSys, is versatile enough to be used for digital
signal processing tasks such as the ones encountered in wireless
communications and sonar processing. DARPA and NSF fund the MorphoSys
project (total support $1.5 million). Dr. Bagherzadeh was the Chair of
Department of Electrical and Computer Engineering in the Henry Samueli
School of Engineering at University of California, Irvine. Before
joining UC, Irvine, from 1979 to 1984, he was a member of the technical
staff (MTS) at AT&T Bell Laboratories, developing the hardware and software
components of the next-generation digital switching systems (#5 ESS).
Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of
Texas at Austin. As a Professor, he has published more than a hundred
articles in peer-reviewed journals and conference papers in areas such as
advanced computer architecture, system software techniques, and high
performance algorithms. He has trained hundreds of students who have
assumed key positions in software and computer systems design companies in
the past twelve years. He has been a Principal Investigator (PI) or
Co-PI on more than $2.5 million worth of research grants for developing
next-generation computer systems for solving computationally intensive
applications related to signal and image processing.
3:30 pm - 3:50 pm
3:50 pm - 5:30 pm
Panel: Configurable CPUs/DSPs for SoC Platform Design
Ron Wilson, Editor, EE Times.
Ron Wilson is Semiconductor Editor at EE Times. Wilson has covered
semiconductors, chip design and related issues for EE Times for 13 years,
with occasional brief diversions such as editing and publishing ISD
magazine. In prior lives he pursued careers in marketing management,
technical training and design engineering, obviously without catching any of
them. He has a list of publications and speaking engagements too
insignificant to mention.
Chinh Le, CEO and CTO of LeWiz Communications
LeWiz Communications Inc. develops SoC chips to solve I/O performance and
security bottlenecks in computing subsystems. Mr. Le is a leading
expert in embedded and network processors. Prior to LeWiz
Communications, Mr. Le was the Director of Engineering for a Silicon Valley
startup company where he successfully led multiple teams to develop complex,
deep submicron network processors and classification engines. Mr. Le
also served as Operations Manager for Motorola Semiconductor and was one of
the original architects of the embedded PowerPC™ processor chips for
Motorola. Mr. Le currently holds nine patents. He also authored
several papers on embedded processor architecture and applications. He
has MSEE and BSEE degrees from Worcester Polytechnic Institute.
Panel: Configurable CPUs/DSPs for SoC Platform Design
Moderator: Ron Wilson, Editor, EE Times.
David Fritz, Vice President of
Marketing for SoC,
Steve Leibson, Technology Evangelist, Tensilica
Professor, Department of Electrical and Computer Engineering, UCI
Ralph Weir, Director of Technical Marketing,
Chinh Le, CEO and CTO, LeWiz Communications
5:30 pm - 8:00pm
Exhibition Room Open
1st International System-on-Chip
Detailed Program Information for Tuesday, April 20, 2004*
7:45 - 8:00
Zaidi, CEO of Palmchip Corporation and Member, Savant Board of Advisors
Jauher Zaidi is Chairman & CEO
of Palmchip Corporation. Jauher has over twenty years of experience in
system design and integration. Before founding Palmchip in 1996, he was
involved in system-on-chip (SoC) integration at Quantum Corporation. Jauher
received his BSEE and MSEE degrees from Pacific States University in Los
Angeles, California. He has also participated in many SoC panels and is a
recognized expert in the area of SoC development.
8:00 am - 10:00 am
SoC Design Using
Programmable ICs & Structured ASIC
Terrill, Senior Manager, Higher Volume Solutions, Xilinx Corporation
Challenges and Opportunities for Programmable Devices at 90nm and Below"
spearheaded adoption of 90nm and 300mm manufacturing technologies, leading
to some of the greatest cost reductions in recent semiconductor history.
Xilinx delivered the world's first 90nm FPGA in March 2003, which combines
90nm/300mm's low costs with the re-programmability and system-on-chip
features of platform FPGAs. Xilinx's Richard Terrill will describe some of
the challenges, trends, and opportunities for design engineers as they
consider FPGAs for applications previously reserved for ASICs and FPGAs. He
will include technical descriptions of FPGAs used in high-volume SoC
applications. He will also provide insight into what lies ahead for Xilinx
and the industry as platform FPGAs add even more capabilities to solve
system level challenges.
Richard Terrill, Senior Manager of High Volume Products Marketing,
has more than 15 years’ experience in the semiconductor and EDA industries,
with responsibilities ranging from technology research to strategic
marketing and business development. Prior to Xilinx, Mr. Terrill held
positions at Lightspeed Semiconductor, Cadence Design Systems, and Altera
Corporation. He was a founder of RAPID, the IP Business Advocacy
organization, and a corporate representative to the VSI Alliance. Mr.
Terrill earned a B.S. degree in Physics from Rensselaer Polytechnic
Institute and served as an officer in the U.S. Army Reserve for six years.
Phillip LoPresti, Associate
Vice President and General Manager, Custom LSI Solutions, NEC Electronics
to Achieve ROI in 90nm ASIC Development"
conditions in the semiconductor market present ASIC designers with a
seemingly impossible task: develop a high-performance
ASIC with minimal NRE investment and very short turn-around time. Truly
high-performance ASICs are certainly possible when implemented in 90nm
process technologies, but 90nm ASIC designs can be so complex that bringing
a product to market quickly enough to generate the huge ROI required to
justify the product's development is increasingly difficult. However, the
introduction of structured ASICs has provided designers with
an ASIC design platform that meets the disparate goals of high performance
ASIC design with low-cost and short turn-around. NEC Electronics America's
Phill LoPresti will explain how structured ASICs, like those in NEC
Electronics' ISSP90 family, are accelerating the ROI for 90nm development.
LoPresti is associate vice president and general manager of the Custom LSI
Solutions strategic business unit at NEC Electronics America. In this role,
he is responsible for expanding the company’s ASIC technology business in
North America. Mr. LoPresti joined NEC Electronics America in 1984 as an
engineer in the company’s design center and later was promoted to manager.
Subsequently he was general manager and then business operations manager of
the system LSI organization, where he was responsible for all system LSI
products and sales. Earlier in his career, Mr. LoPresti was employed by RCA
Automated Systems and also was an adjunct professor of electronics at
Northeastern University in Boston, Massachusetts. He holds both bachelor of
science and master of science degrees in electrical engineering from Boston
Shyam Chandra, Marketing
Manager, Lattice Semiconductor Corp.
Power Supply Management Using an Integrated Programmable Mixed Signal
Satisfying the power supply
tracking and sequencing requirements of all multi-voltage devices on a
circuit board coupled with supervising the health of all supplies, called
Power Supply Management, is both parametrically demanding and logically
challenging. This paper breaks down the challenges and identifies the
requirements of a circuit board’s power supply management section and shows
how the revolutionary integrated mixed signal device with design software
provides unprecedented convenience to the design engineers.
is the Marketing Manager for the in-system programmable mixed signal
products at Lattice Semiconductor Corp. Prior to joining Lattice, he worked
for Vantis and AMD in sales and applications and was a telecom design
engineer with Indian Telephone Industries. Shyam received his Master's
degree in Electrical Engineering from Indian Institute of Technology,
Ganesh Narayanaswamy, Product Marketing Manager, Altera
"Maximizing the Possible Benefits of Structured ASIC
The rising costs of semiconductor manufacturing, coupled with
growing design complexities resulting from increasing integration, have
combined in the last few years to dramatically raise both the risks and the
costs involved in designing and developing application-specific integrated
circuits (ASICs). Today, cost of ownership for the development of a
single ASIC device can be as high as $20 million before the first samples
are delivered. As a result of these economic and technical challenges,
a number of companies have developed a “structured ASIC” manufacturing
approach designed to reduce the costs, risks, and development time involved
in producing custom ICs. This paper will discuss the factors that have
led to the rise of structured ASICs and that are increasingly limiting the
cost-effectiveness of the traditional ASIC approach. It will also
describe what is needed to make a structured ASIC design succeed and the
methodologies and approaches necessary to maximize the benefits promised by
this emerging technology.
Narayanaswamy joined Altera in 2002 as a Product Marketing Manager
responsible for the HardCopy structured ASICs product line. Prior to Altera,
Ganesh held several engineering and managerial positions at National
Semiconductor, Insilicon and Sanmar Electronics. Ganesh holds an MS from
Mississippi State University and an MBA from Santa Clara University.
10:00 am - 10:15 am
-- Coffee Hosted by Toshiba
10:15 am - 12:15 pm
Venable, Senior Vice President, Palmchip Corporation
a System-on-Chip Platform Methodology in the Design Flow Requires a New Way
presentation outlines the definition of an SoC platform and how implementing
an SoC platform methodology within the design flow requires the engineer to
rethink his/her approach to chip design by considering the entire process,
from concept through the front-end process to the back-end process and
eventually to manufacturing. The presentation will also discuss how this new
approach to SoC design dramatically increases the chance of first-silicon
success, reduces the time needed to get a chip to market, and reduces design
cost to increase profitability.
Jim Venable is a
Senior Vice President at Palmchip with overall responsibility for marketing
and sales. He is a 20-year veteran of the semiconductor industry and has
served at senior management levels with global leaders in semiconductor and
microelectronics products. Jim holds a BS in electrical engineering from
Texas Tech University.
Lakshmi Mandyam, PowerQUICC III Product Manager
"Implementing a System-on-Chip Platform for High-Performance Communications
processors" are defined as highly integrated processors (computing devices
executing a set of user-programmable instructions) specifically optimized
for communications and networking applications (voice/data/video;
data/control/management planes). This presentation will focus on
communications processors that are based on System-on-Chip (SoC) platforms,
which make it faster and easier to integrate various processing blocks,
industry-standard peripherals, interfaces, buses and protocol support to
address specific customer and market needs. A case in point is Motorola's
32-bit, RISC-based PowerQUICC III communications processor family. The
PowerQUICC III SoC architecture features an array of industry standards and
Motorola technologies, including a high-performance Book E PowerPC e500
core, 256KB on-chip L2 cache, a RISC-based Communications Processor Module (CPM)
for protocol acceleration, RapidIO interconnect technology, dual Gigabit
Ethernet interfaces, and support for DDR SDRAM and PCI/PCI-X. PowerQUICC
processors feature a four-port, packet-based crossbar switch fabric that
enables high-bandwidth on-chip communications, execution of multiple
simultaneous data transactions and peer-to-peer transactions with CPU
intervention. PowerQUICC III processors are also available with an
integrated security engine that supports DES, 3DES, MD-5, SHA-1, AES, and
ARC-4 encryption algorithms, as well as a Public Key accelerator and on-chip
Random Number Generator. PowerQUICC III processors are manufactured on
Motorola's 130nm processor technology, and 90nm versions are planned for the
future. The PowerQUICC III family is supported by a comprehensive ecosystem
of development tools (reference and evaluation boards, application
development systems, software tools, RTOSs, etc.) from Motorola and
is a PowerQUICC III Product Manager at Motorola's Networking and Computing
Systems Group in Austin, Texas. She is responsible for all facets of product
management and product marketing for the next-generation PowerQUICC III
communications processor with RapidIO technology. During her 10-year tenure
at Motorola, Lakshmi has served as an SRAM product engineer, worked in
PowerPC processor marketing roles, and was instrumental in developing
Motorola's security processor strategy and product implementation. She holds
a B.S.E.E. from the University of Texas at Austin.
System Engineering Manager
for Toshiba America Electronic Components, Inc.
SoC: From System- to Solution-on-Chip"
System-on-Chip (SoC) has
always been equated to a piece of silicon. However, delivering a working
piece of silicon is just half the job. Successfully porting or writing
software such as device drivers and RTOSs to the new piece of silicon is a
long, arduous journey. The market is unforgiving to those who cannot deliver
a complete solution on time. From a market standpoint, shrinking product
life cycles, and a highly demanding customer constitute two, ever-present
challenges. Players such as Toshiba have seized the opportunities and have
responded to the market challenges with their ability to deliver in record
time -- not just silicon -- but a complete package comprising both software
and hardware. To put that in perspective, it is practically possible to
deliver a silicon solution from a block diagram in 6 months -- i.e., a
working piece of silicon plus RTOS, IP drivers, middleware and chip
diagnostics ported to the platform. This session traces and analyzes how the
SoC has come to stand for "Solution-on-Chip" (i.e., a complete silicon
solution rather than just a piece of silicon) and how teams at Toshiba are
able deliver a complete solution in record time. The session ends with ideas
for the audience on how this approach can make business sense to sponsors
and managers of SoC projects in their respective organizations.
Sundaram is System Engineering Manager for the System LSI Group of Toshiba
America Electronic Components, Inc. (TAEC). He has 10 years of experience in
various engineering and marketing roles in the semiconductor, telecom, and
IT industries. He holds a Master's degree in Business Administration from
Thunderbird (American Graduate School of International Management) and a
BSEE degree from Birla Institute of Technology and Science (India).
(Raj) Singh, Senior Marketing Manager, LSI Logic CoreWare Technology Group
SoC Design Using RapidChip Platform ASIC with System CoreWare IP"
Over a decade ago, LSI Logic’s pioneering
efforts in IP reuse revolutionized ASIC design by establishing a proven
CoreWare IP portfolio. CoreWare set the standard in the industry with
its rich set of proven, easy-to-integrate, and performance-leading cores.
LSI Logic recently introduced System CoreWare, which extend its IP platform
capabilities. By raising the level of abstraction from component IP to
pre-defined, pre-verified systems that are modular and easily extendable,
System CoreWare IP significantly lowers the risk and design time associated
with developing complex custom SoCs. When used in conjunction with RapidChip
silicon platform and the associated RapidWorx design system, this provides a
totally new and innovative way to manage complexity and meet the shortened
time-to-market goals for developing custom ICs.
Balraj (Raj) Singh is a Senior Marketing Manager in LSI
Logic’s CoreWare Technology Group. His responsibilities include strategic
marketing of CoreWare IP and product definition, including definition of
processor systems and platforms. Prior to his current role, Raj has worked
in various engineering and management roles at LSI Logic, Siemens
Microelectronics, and Hewlett-Packard. While at Siemens, Raj played a
key role in micro-architecture development and VLSI design of the first
TriCore MCU/DSP. At Hewlett-Packard, Raj was responsible for
micro-architecture performance analysis for the PA-RISC and IA-64 based
processors. Raj holds a BS in Electrical Engineering and Computer
Sciences from the University of California at Berkeley and an MS in
Electrical Engineering from Stanford University. He has multiple
patents and papers in the microprocessor field.
12:15 pm - 1:15 pm
1:15 pm- 1:45 pm
CEO and President, iSuppli
Realities Mandate Fundamental Changes in Competitive Strategies"
past several years of downturn and weak recovery, the foundations of the
semiconductor business have been dramatically altered, which in turn will
cause changes in the nature of the industry's unit growth and price
dynamics, requiring very different strategies for success on the part of
chip suppliers. The rules of thumb developed by successful semiconductor
executives over the past 30 years don't apply anymore--and can't yield the
same kind of success they did previously.
iSuppli to provide the visibility, resources, and control to improve the
electronics industry value chain. iSuppli accomplishes this by gathering and
disseminating unique value chain data and information and by working with
its clients to use the information to make better and faster business
founding iSuppli, Derek was CEO of International Rectifier, a leading power
semiconductor company. Derek earned a BSEE degree Summa Cum Laude from
Princeton and a Ph.D. in Applied Physics from Stanford as a Hertz Foundation
1:45 pm- 2:15 pm
Vice President of Marketing and
Business Development, Xiran
Processing Platform for IP Storage and Content Delivery Applications"
Division of SimpleTech Inc., is a leader in Content Delivery and IP Storage
acceleration cards technology. Our core competency as a system
solution technology provider is based on our DirectPath Engine (DPE), a
symmetric multiprocessing system on a chip (SoC) showcasing the highest
level of integration applied to configurable and programmable processors and
dedicated logic solving systems I/O bottlenecks. As the name implies,
we create a DirectPath between network and storage nodes of the general
purpose server or storage hosts and offer up to 10x performance enhancement
to upgraded systems with our accelerator cards. We achieve this
performance by increasing the serverwidth of server or networked
storage systems, where Xiran's SoC-based accelerator cards offer efficient
delivery of content and data between network and storage nodes of these
systems. In summary, we will discuss how we are able to solve complex
problems of separating control plane and data plane traffic of systems
leveraging from our SoC centric technology.
A 20-year high
technology veteran, JeanClaude Toma has held several executive-level
positions as President and C.O.O. of NKK Micro Devices, Senior Director at
Toshiba America, as well as several Business Development, Marketing and
System Engineering roles in Unisys, American Arium, and other companies. Mr.
Toma has an MSEE and an MBA from Cal Poly Pomona and a BSEE from UC Irvine.
2:15 pm - 4:15 pm
EDA Tools and
Director, Cadence Synthesis Team
"Front-end Design for
Abstract: The focus of
this talk is to highlight the need for next generation front-end EDA
solutions for designing nanometer SoCs. Over the course of the last decade,
significant improvements in the back-end tools, combined with a lack of
innovation in the front-end technology, has resulted in the front-end design
becoming the weakest link in SoC designs. This paper presents the idea
behind the globally-based optimization algorithms necessary for making
design closure easier and provides case studies to support the suggested
rules for creating designs with superior Quality-of-Silicon (QoS)
a Director on the Cadence Synthesis team. In that role he is focused on
marketing the solution for the best Quality-of-Silicon (chip speed, area,
power, test measured after wires). Carlson reports to Chi-Ping Hsu,
Corporate VP for New Synthesis at Cadence. Steve joined Cadence in April in
2003 via the Get2Chip acquisition, where he was the VP of Marketing. Prior
to Get2Chip, Steve was the CEO of Tharas Systems, a hardware acceleration
company. Steve has also held various management positions at Escalade, LSI
Logic, United Technologies and Synopsys. At Synopsys, Steve was a part of
the original Design Compiler technical team responsible for timing analysis
and optimization. Steve was the author of the industry’s first book on
high-level design titled, Introduction to HDL-based Design Using VHDL.
Steve has BSEE and BSCS and an MSEE all from the University of Colorado.
Jones, Director, Strategic Marketing, Magma's Silicon Correlation
Modeling Challenges for 90nm"
Design teams are
adopting 90nm process technologies to build System-on-Chip designs under
fiercely competitive market pressures against the constraints of power,
packaging, timing, and die size. These teams are building new power-aware
methodologies around a growing set of new design styles and EDA tools.
However, fundamental power modeling issues and requirements must be
understood before these advanced methodologies can be incorporated
effectively into production SoC design flows. This session presents a
background on these power modeling challenges, an overview of the low-power,
multi-threshold and multi-voltage design techniques new to most designers,
followed by a discussion of associated requirements necessary to be
successful in complex 90nm SoC design.
Jones is director of strategic marketing for Magma’s Silicon Correlation
Division, formerly Silicon Metrics. With over 19 years in the semiconductor
and EDA industries, he drives the division’s corporate planning, strategic
business development and corporate marketing. Prior to joining Silicon
Metrics, he held various technical and management roles at Synopsys, Avanti,
System Level Design Specialist
Tools for SoC High-Level Design and Verification"
Today, SoC presents a new
design methodology in which competitive advantage is moved into IP and SW
integration, rather than pure HW design. The challenges depend upon an
ability to compose a set of pre-defined HW blocks--including one (or
several) processors, bus, memory, peripherals and SW--into an optimized
architecture that can perform complex tasks. With the new ESL tools,
users can model complex systems with abstract data objects and communication
interfaces--and quickly analyze functional and architecture
characteristics--long before HW and SW implementation start. The ability to
"floor plan" SoC architecture is highly important in the effort to optimize
resources that directly impact cost and power. Detecting high level
communication faults (HW/HW and HW/SW) at such an early stage significantly
reduces the RTL verification cycle, as well as the overall
product design cycle.
Dave Apte has 12 years of
experience in EDA tool development and technical marketing. He held senior
technical positions at Omniview, Viewlogic and Innoveda, and is currently
product manager for Summit Design's System Architect. Dave has managed the
development and marketing of system-level design tools based on HDLs and
SystemC. He has previous experience in the development of semiconductor
device and process simulators and design-capture tools. He holds bachelors
and masters degrees in electrical engineering from the Indian Institute of
Technology, Bombay, and a masters from the University of Florida.
Santos, Product Manager, Synchronicity
SoC Design Productivity Through Systems That Support Effective Reuse"
Semiconductor manufacturing advances are enabling
feature-rich systems on one chip, but with traditional design practices
engineering costs are prohibitive, so design organizations are scrambling to
do all they can to improve productivity and speed time to market.
Though it’s taken almost a decade to fulfill its early promise, massive
design reuse, from both internal and external IP sources, is proving to be
the single most effective way to raise productivity--but only for those who
put proper processes and supporting infrastructure in place. We are
going to examine the challenges to reuse in SoC design, the requirements for
systems to support it, and solutions available, including advanced
hierarchical management solutions for block-based design.
Pedro Santos is
Product Manager for the Synchronicity Publisher Suite, the industry’s most
widely adopted solution for design reuse, IP distribution, and support.
Before joining Synchronicity, Pedro held a similar position at Genuity,
where he was central in making Genuity's e-Business Collaboration product
line a success. Pedro has also implemented various engineering design
management systems at high tech companies. Pedro has an engineering
degree from the University of Massachusetts.
4:15 pm - 4:30 pm
4:30 pm - 6:00 pm
Panel: EDA Tools for 90nm and Post-90nm
Dave Bursky, the Editor-at-Large for Electronic Design magazine,
joined Electronic Design in 1973, and has worked in various editorial
positions, amassing more than 30 years of experience covering technology and
product developments in the electronics industry. Promoted to
Editor-in-Chief in the fall of 1999 and to Editor-at-Large in early 2003, he
has been responsible for defining the direction and content of Electronic
Design. In addition to the editorial management responsibility, he has
covered all aspects of Digital Semiconductor Technology, from processes to
architectural definition, and from testing to circuit applications, for the
magazine. He travels extensively around the
U.S. as well as
to Asia and Europe to interview company executives, and to attend trade
shows and symposiums.
Additionally, Dave is one of several Electronic Design editors
awarded the Jesse H. Neal award for Editorial Excellence. In 1988 he was
described by an article in the San Jose Mercury News newspaper as one of the
100 most influential people in Silicon Valley. He has also taught digital logic technology at
the former RCA Institute in
New York City,
and has been a guest lecturer at the
Post-Graduate School in Monterey, Calif.. Additionally, he has served on the
program committees of numerous IEEE and commercial conferences, and has also
moderated and organized technical presentation sessions at IEEE and
commercial conferences. He has also authored six books on topics ranging
from personal computers to semiconductor memories.
Prior to joining Electronic Design in 1973, he worked as a
civilian electronics engineer at
N.J. on tactical computer systems and secure communication systems. Dave
holds both Bachelor's and Master's degrees in Electrical Engineering from
the City College of the City University of New York (1971 and 1973,
Dave lives in
and is married and has two children. In his spare time, he enjoys reading,
stamp collecting, electronics (home-brew computing), and traveling.
Martine Simard-Normandin, President and CEO, MuAnalysis
Simard-Normandin has over 26 years' experience in microelectronics,
device physics, process modeling, microcontamination
and electrical and material characterization.
During that time she has authored or co-authored over 50 scientific journal
and conference papers on microanalysis. Previously, Dr. Simard-Normandin was
Manager of the Materials and Device Analysis Department in
STMicroelectronic’s Centre for Microanalysis, and Manager of Materials and
Structures Analysis at Nortel Networks. She founded MuAnalysis in 2002. Dr.
Simard-Normandin holds a B.Sc. in physics from
the Université de Montréal and
Ph.D. in astronomy from the University of Toronto.
was awarded an Industrial Postdoctoral Fellowship from the American Physical
Society, focusing on microelectronics.
Dr. Mahmoud F. Wagdy, Professor of Electrical Engineering, California
State University, Long Beach
Dr. Mahmoud Fawzy Wagdy, Professor of Electrical
Engineering, California State University, Long Beach (CSULB). He received
the B.Sc. and M.Sc. from Cairo University in 1973 and 1977 respectively, and
the Ph.D. from Kansas State University in 1983, all in electrical
engineering. He worked in Cairo in the Electronic Industries R&D Center
(1973-76) and the Electronics Factory, Arab Organization for
Industrialization (1977-79). He spent 4 months in 1977/78 at Thomson-CSF in
France. Prior to joining CSULB in 1989, he worked in Boston (Northeastern
University & University of Massachusetts at Lowell) as Assistant Professor.
Dr. Wagdy’s present teaching interests include undergraduate and graduate
courses in microelectronics, mixed-signal integrated circuit design, analog
signal processing, design of electronic systems, etc. Dr. Wagdy’s recent
research includes mixed-signal IC design and switched-current analog signal
processing. Previous research includes A/D converter diagnosis, dithering,
and switched-capacitor techniques. Old research includes computer-based
measurements and active-R filters. He has held summer positions at Analog
Devices Semiconductors (Wilmington, MA) and the Jet Propulsion Laboratory
(Pasadena, CA). He was sometimes involved in consulting. He has worked on
many funded research projects including a college-level NSF project, where
he produced multimedia modules on electronics manufacturing and interference
signal reduction. He is the founder and director of the electronics and
instrumentation research laboratory in the EE Department. Dr. Wagdy has
published about 43 papers in journals and international conferences and his
research has been cited internationally over 130 times. He is the recipient
of the Andrew Chi Best Paper Award for his 1989 paper on ADC dithering in
the IEEE Transactions on Instrumentation and Measurement (I&M). Dr.
Wagdy served as a Guest Editor for the special issue of the IEEE
Transactions on I&M in 1994. He was the Technical Program Chairman of the
IEEE Instrumentation and Measurement Technology Conference (IMTC/1993). He
also served as Chairman of the IEEE Los Angeles joint chapter on I&M and
Industrial Electronics (1992-96). He was a member of many committees at the
department, college, and university levels. He is also the preparer of the
ABET-2000 Self Study for the EE Department.
John A. Ford, Vice President of Marketing,
John A. Ford
is Vice President of Marketing for Virtual Silicon, a ventured back start-up
Semiconductor Intellectual Property (IP) company located in Sunnyvale, CA.
John brings to Virtual Silicon an extensive background in engineering and
marketing of ASIC and system-on-chip (SoC) semiconductors. He previously
held the position of Director of ASIC/SoC Marketing at Atmel. During his 11
years at Atmel, John started the ASIC product line, and led the strategic
product development, business development and acquisition efforts for
ASIC/SoC product division. Prior to joining Atmel, John held management
positions in both marketing and engineering at General Electric and
Honeywell. John holds a BS in engineering from the University of
Massachusetts, Amherst and an MBA from the University of Colorado.
Panel: "EDA Tools for 90nm and Post 90nm"
Director, Cadence Synthesis
2) Robert Jones,
Director, Strategic Marketing, Silicon Correlation Division,
Ford, Vice President of Marketing,
4) Dr. Wagdy, Professor of Electrical and
Computer Engineering, CSU Long Beach
Martine Simard-Normandin, President and CEO, MuAnalysis
6:00 pm - 6: 15 pm
Closing Remarks -- Farhad
Mafie, Savant Company Inc.
*Subject to change.
Savant Company Inc. reserves the right to revise or modify the above program at
its sole discretion.
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