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6th International
System-on-Chip (SoC)
Conference, Exhibit &
Workshops
November 5 & 6, 2008
—
Radisson Hotel Newport Beach, Southern California
The Most Informative, Targeted, and Affordably
Priced
SoC, ASIC, ASSP, CSSP, FPGA, and Foundry Technology Conference &
Exhibit Event of the Year!
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Program Summary
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SoC Conference Day 1 |
Wednesday, November 5, 2008 |
8:00 am - 6:30 pm |
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SoC Conference Day 2 |
Thursday, November 6, 2008 |
8:00 am - 7:00 pm |
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SoC Tabletop Exhibit |
Wednesday, November 5, 2008 |
4:30 pm - 8:30 pm |
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SoC Workshops |
Check the Individual
Workshop Schedules |
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Conference Program Agenda* |
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Day One
Wednesday
November 5
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Session |
Company
or
University |
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7:00 am –
6:00 pm |
Registration
Open All Day |
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8:00 - 08:15 |
Welcome,
Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.
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Savant |
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8:15 – 12:00 |
New
Trends, Technologies, Methodologies, and Products for Your Next Chip Design
Track
Chairman: Dr. Goran Matijasevic is Director of Research Development at The
Henry Samueli School of Engineering at UC Irvine |
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8:15 – 8:45 |
Semiconductor
SoC, ASIC, FPGA Market update. Jordan Selburn, Silicon Analyst |
iSuppli |
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8:45 – 9:15 |
Analog
Integration in Complex SoCs. TBD |
Jazz
Semiconductor |
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9:15 – 9:45 |
Leveraging
ESL Technologies for Low-Power Design, Jon McDonald - Senior Technical
Marketing Engineer, ESL and Design Creation Division. |
Mentor
Graphics |
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9:45 - 10:00 |
Morning Break
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10:00 – 10:30
Keynote |
Keynote:
"Circuits with Light at the Nanoscale."
Dr. Nader Engheta, Professor of Electrical and Systems
Engineering, and Professor of, Bioengineering. |
University of
Pennsylvania |
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10:30 – 11:00 |
FPGAs at
the 45nm process node and beyond, Dr. Mojy Chian, Vice President of
Technology Development. |
Altera |
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11:00 – 11:30 |
Advanced Power Management
Techniques, Mark Barry, Technology Innovation Manage. |
Silicon & Software Systems |
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11:30 – 12:00 |
Achieving the
Need for Speed in Flash Based Designs. Jim Cooke,
Staff Architect and Technologist, NAND Flash. |
Micron Technology |
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12:00 pm -
1:00 pm |
Lunch
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1:00 - 2:00
Panel |
Panel:
“Hardware
and Software Challenges for Multicore SoCs in Leading-Edge Applications”
Moderator:
Robert Cravotta, Technical Editor, Microprocessors, DSPs, Software,
and Tools, EDN Worldwide.
Panelists:
1:
Steve Leibson, Technology Evangelist.
2: Jack Harding, Chairman,
President and CEO.
3: Peter Ehlig, P.E., Fellow DSP,
Semiconductor Group.
4: Dr. Dan Shimizu, AMD Fellow.
5: Glenn Perry, General Manager,
ESL and Design Creation Division.
6: TBD
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EDN
Tensilica
eSilicon
Texas Instruments
AMD
Mentor Graphics
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2:00 – 2:30
Keynote |
Keynote:
Rose Schooler is general manager of the Performance Products
Division in Intel’s Embedded and Communications Group. |
Intel |
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2:30 – 6:00 |
Hardware
and Software Challenges for Multicore SoCs in Leading-Edge Applications
Track
Chairman: Farhad Mafie, Savant Company Inc. |
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2:30 – 3:00 |
Convenient Concurrency Rules Multicore SOC Design, Steve Leibson, Technology
Evangelist. |
Tensilica |
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3:00 – 3:30 |
Venezia, A
New Scalable Multicore Processor for Mobile Multimedia Applications. Hideki
Takeda, Senior Specialist,
Center for Semiconductor Research & Development Semiconductor Company
Toshiba Corporation. |
Toshiba |
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3:30 – 4:00 |
Design of
A VLIW/SMT/Dual-Core SWP-SIMD PLX2 Processor.
Professor Sao-Jie Chen. |
National
Taiwan University |
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4:00 – 4:15 |
Afternoon
Break |
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4:15 – 4:45 |
Scalable
Video Platform Enabling HD Video Communication, Dr. Thanh
Tran, Senior Member Technical Staff. |
Texas
Instruments |
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4:45 –
5:15 |
General Purpose Processors
(GP) vs. Application Specific Processors (ASP), what is the future for
multicore designs with 1000's of IPs? Dr. Nader Bagherzadeh, professor of
computer engineering in the department of electrical engineering and
computer science, University of California, Irvine. |
UCI |
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5:15 – 5:45 |
Boosting System Performance
with Multithreaded Multiprocessing.
Gideon Intrater, Vice President of
Solutions Architecture. |
MIPS
Technologies |
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5:45 – 6:15 |
Is The "True
NoC" Just An Urban Engineering Legend? Antonio-Marcello Coppola, Head of the Grenoble Research Laboratory. |
ST
Microelectronics |
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4:30 pm -
8:30 pm
Exhibit
Reception |
Conference Exhibit & Reception Open
(Free
Exhibit Pass) |
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Day Two
Thursday
November 6
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Session |
Company
or
University |
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7:00 am –
7:00 pm |
Registration
Open All Day |
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8:00 - 8:15 |
Welcome,
Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.
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Savant |
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8:15 – 12:00 |
Innovative
Embedded Memory Solutions for Complex Multicore SoCs
Track
Chairman:
Dr.
Nader Bagherzadeh,
University of
California, Irvine.
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8:15 – 8:45 |
NVM
Technologies - B4-Flash with its Embedded Application and eCFlash (Logic NVM
IP) Moriyoshi Nakashima, President.
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GENUSION |
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8:45 – 9:15 |
Demystifying
Logic NVM Options. Craig Rawlings, Director of Marketing. |
Kilopass Technology |
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9:15 – 9:45 |
Z-RAM: A
Better DRAM, Jeff Mitchell, Director of Technical Marketing. |
Innovative
Silicon |
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9:45 – 10:00 |
Morning Break
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10:00 – 10:30
Keynote |
Keynote: "An
All Silicon 3D Systems Technology, An Emerging and Disruptive Technology for
Convergence of IC, Package and System," Professor Rao R. Tummala, Director
of Microsystems Packaging Research Center. |
Georgia Institute of Technology |
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10:30 – 11:00 |
Embedded
Memory IP Challenges. Dr.
Raymond Leung, Vice President of Memory IP Development. |
UMC |
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11:00 – 11:30 |
Using Data
Traffic Efficiency Metrics to Select the Best DDR Memory Controller for your
Design. Luigi Ternullo, Product Marketing Manager,
STAR Memory System. |
Virage Logic |
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11:30 – 12:00 |
Innovative
1T Embedded Memories, Dr. Gil Winograd, Chief Operating Offices & Co-Founder.
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Novelics |
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12:00 – 1:00 |
Lunch
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1:00 – 2:00
Panel |
Panel:
“Innovative
Embedded Memory Solutions for Complex Multicore SoCs”
Moderator:
John E. Blyler, Editorial Director Chip Design, Embedded Intel, Green
Embedded and EE Catalog magazines.
Panelists
1:
Dr. Cyrus Afghahi, CEO, Novelics.
2: Dr. Dick Foss, Founder and
former Chairman of MOSAID.
3: Dr. Azeez J. Bhavnagarwala, Low
Power Circuits & Technology, IBM TJ Watson Research Center.
4:
TBD
5: TBD
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Chip Design
Novelics
MOSAID
IBM
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2:00 – 2:30
Keynote |
Keynote:
Joachim Kunkel, VP and General Manager, Solutions
Group. |
Synopsys |
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2:30 – 5:45 |
Innovative EDA Tools for Complex SoC Designs in 45nm and beyond.
Track Chairman: Dr. Jim Lipman, Vice President, Cain Communications
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2:30 – 3:00 |
A ROI
Model for Electronic System Level (ESL) Methodology, Glenn Perry, General
Manager, ESL and Design Creation Division. |
Mentor Graphics |
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3:00 – 3:30 |
ESD Design
Challenges in nano-CMOS SoC Design, Benjamin Van Camp, Director of
Engineering. |
Sarnoff Europe
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3:30 – 4:00 |
ESL
modeling and simulation for SoC architecture and performance estimation.
Vincent Perrier is CoFluent Design's co-founder and director.
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CoFluent Design |
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4:00 – 4:15 |
Afternoon
Break |
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4:15 – 4:45 |
Bill
Neifert, Chief Technical Officer - Founder, VP Business Development. |
Carbon Design Systems |
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4:45 – 5:15 |
CyberWorkBench: Integrated Design Environment Based on C based Behavior
Synthesis and Verification, Dr. Kazutoshi Wakabayashi. |
NEC
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5:15 –
5:45 |
Scaling
Verification with the Open Verification Methodology (OVM),
Thomas L. Anderson,
Product Marketing Director.
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Cadence Design Systems |
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5:45 – 6:45
Panel |
Panel:
“Technology &
Entrepreneurship . . . Dreams, Realities & Opportunities”
Moderator:
TBD
Panelists
1:
Jauher Zaidi, President
& CEO, PalmChip
2:
R Sampath, Chair, IEEE Orange County Section
3:
Dr. J. Antonio Carballo, Partner, IBM Venture Capital Group, Corporate HQ
Division.
4:
TBD
5:
TBD
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PalmChip
IEEE OC Chapter
IBM
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6:45 – 7:00 |
6th
International SoC Conference Closing Remarks. Farhad Mafie, President & CEO.
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Savant |
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* Program is subject to change.
Savant Company Inc. reserves the right to revise or modify the above program at
its sole discretion.
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