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6th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

November 5 & 6, 2008 — Radisson Hotel Newport Beach, Southern California

The Most Informative, Targeted, and Affordably Priced

SoC, ASIC, ASSP, FPGA, and Foundry Technology Conference & Exhibit Event of the Year!

Conference Program Abstracts & Bios*

8:00 - 8:15

Savant Company Inc.

Farhad Mafie, President and CEO of Savant Company Inc.

"Welcome and Opening Remarks, Technology/Market Trends."

Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models.

Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis.  He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company.   Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.  His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies.  Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

8:15 am - 12:00 am

New Trends, Technologies, Methodologies, and Products for Your Next Chip Design

Track Chairman: Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine

Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine

Bio: Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. In this capacity, he works on formation of new industry-university and academic collaborations, especially focusing on new interdisciplinary research initiatives. Prior to this, he was the Research Coordinator of the Integrated Nanosystems Research Facility at UC Irvine, where he worked closely with industry partners on making them aware of available university resources. Prior to UCI, he worked as a senior engineer at QPlus, a telecommunications start-up company. From 1994 to 2001, he was at Ormet Technologies, where as Director of Research he was working on development of polymer and metal materials and structures for electrical interconnect of high density circuits, new metal alloys for use in conductive adhesives, materials for embedded passive components and heat sensors, and high thermal efficiency electronic substrates. ¨He managed multiple SBIR projects that led to several industry consortia projects, as well as a license agreement with a Fortune 100 company. He has 4 U.S. patents, 3 book chapters, and over 40 conference and journal publications and has served on the NEMI Industry Roadmap committee. He served as NanoWorld Conference Technical Chair, the Electronic Components and Technology Conference (ECTC) Interconnect Chair and Emerging Technologies Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing Committee. He is currently on the OCTANe (Orange County Technology Action Network) Operations Committee and Vice Chair of OC Innovation. Goran received his PhD from UC Irvine in Electrical and Computer Engineering and his MBA from Pepperdine University. He is also a member of the TriTech Advisory Board, Southern California Biomedical Council Board, Tech Coast Venture Network, IEEE, and ASME.

8:15 - 8:45

iSuppli

Jordan Selburn, Principal Analyst, Core Silicon, iSuppli Corp

Bio: Jordan came to iSuppli with decades of extensive experience in ASIC, programmable logic and semiconductor intellectual property (IP) analysis, product marketing, and engineering development. Prior to joining iSuppli, Jordan served as the Director of Product Marketing for Amphion Semiconductor, where he was tasked with managing the technical product marketing team. He launched products in all of Amphion’s product families in addition to providing in-depth sales support for the products and the IP business model. Prior to his tenure with Amphion, Jordan was the Principal Analyst for ASIC and IP at Gartner Group/Dataquest and as such was responsible for the evaluation and analysis of semiconductor IP as well as the ASIC and programmable logic markets. He formulated and presented tracking and forecasting on technology and market trends with particular emphasis on system-level integration as part of his duties at Gartner Group/Dataquest.  Marketing Manager and Product Line Manager positions at LSI Logic preceded his employment at Gartner Group/Dataquest. At LSI Logic, Jordan was charged with establishing product positioning and pricing for their production ASIC products. In addition, he generated technical requirements and provided marketing direction to product development teams along with creating business plans for 0.6 micron and 0.35 micron technologies. Before LSI Logic, Jordan was an ASIC Technology Manager and a Corporate Applications Engineer at Valid Logic Systems/Cadence Design Systems and was also associated with Agilent/EEsof, Inc., and Harris Corporation in various engineering capacities. Jordan holds a Master of Science in Engineering Economic Systems from Stanford University in addition to an MBA with distinction from Santa Clara University and a BSEE with honors from the University of Michigan.

9:15 - 9:45

Mentor Graphics

Jon McDonald - Senior Technical Marketing Engineer, ESL and Design Creation Division, Mentor Graphics.

"Leveraging ESL Technologies for Low-Power Design."

Abstract: Designs for managing and optimizing power are a key concern for today's electronics companies, and the only way to address future power needs is through architecture and functional-aware techniques. Electronic System Level (ESL) design is the only domain that offers a practical platform to address today's power design issues. This 30-minute technical session will introduce a dynamic power management theory , functional-aware optimization, HW/SW tradeoffs, and an approach to design for power, applying available ESL technologies. Included, will be a couple of case-studies to support these key points. This technical session will be of value to SoC developers, HW and SW designers, followed by a Q/A session with the presenter (if available).
 

Bio: TBD.

9:45 - 10:00

Morning Break

Morning Break

10:30- 11:00

Altera

Dr. Mojy Chian, Vice President of Technology Development
Altera Corporation
 

"FPGAs at the 45nm process node and beyond."

Abstract: As semiconductor process geometries advance to 45-nanometer and below, we face significant development challenges both from a technical and business perspective. Factors such as power efficiency and cost of development have increased in significance with each new process generation and are now dominant concerns for design teams. When the required R&D costs for each new process generation are at least 50% higher (i.e. mask costs at 45-nm are over $3M), the focus must be on first silicon to production. To keep development costs down, solving these technical issues can be overcome by using the “comprehend, model and predict” methodology. This in turn will accomplish the goal of realizing a return on R&D investment, meeting time to market requirements, and future-proofing devices, which allows changes to be made later. This forces an ever-increasing number of applications to migrate to from ASIC to FPGA-based designs. Additionally, experiences with 45-nm design shows how techniques such as expanded statistical simulation and methodical testing in silicon throughout the design process are helping developers achieve first-time success in their designs. From a technical perspective new design approaches and techniques are needed to address these design challenges. These key technical challenges include lower voltage headroom, increased process variability, leakage control, ESD, strain induced proximity effect, temperature inversion, and speed to power conversion. How these challenges are being addressed is the key. By closely collaborating with a foundry partner design/process challenges, significant value can be extracted from advanced process technologies. These challenges include sophisticated device modeling that consider all deep sub-micron and proximity effects, statistical simulation and modeling tools to isolate and predict local and global variability, controlling leakage through multiple gate oxide transistors, selective Vt adjustments, and selective channel length adjustments.

Bio: Mojy Chian is vice president of technology development at Altera Corporation. Before joining Altera, he was senior vice president of high-performance analog engineering at Mindspeed Technologies. While there, he was responsible for all aspects of IC product development, as well as leading the core technology group from 2000 to 2004. Prior to this, he was vice president of design automation and IP infrastructure for Conexant Systems, worked at Rockwell Semiconductor Systems, and spent ten years at Harris Semiconductor (later Intersil), leaving as the director of design systems. Mr. Chian received his BS, MS, and PhD in Electrical Engineering as well as an MS in Applied Math from Florida Tech. He holds two US patents, has authored or co-authored over 30 technical publications, and has served as adjunct professor at Florida Tech.
 

11:30 - 12:00

Micron

Jim Cooke, Staff Architect and Technologist, NAND Flash.

"Achieving the Need for Speed in Flash Based Designs."
 

Abstract: One of the most important questions designers are asking today is whether to integrate Flash technology on-chip or move it off-chip. In this presentation, we will discuss the growing acceptance of off-chip NAND Flash technology in embedded applications such as set-top boxes, MP3 players, digital cameras, and new smart cell phones. In the process, we will cover trends, reliability challenges, and advanced new features and security enhancements in NAND technology. We will also explore new possibilities in performance and power trade-offs in the smaller geometries as we move toward mass production on 90nm—and in the near future on 65nm. And finally, we will present packaging trends that present a feasible and promising option to integrating on-chip memory.

Bio: Jim Cooke is a Director of Application Engineering for Micron’s Mobile Memory Group. Prior to joining Micron, he managed the applications engineering group and hardware engineering team for Toshiba America Electronic Components. Mr. Cooke has over 20 years of hands-on systems-level design experience in embedded applications and digital consumer markets. He holds a BSEE from the University of Massachusetts.

11:30 - 12:00

Lunch

Lunch

Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications

Track Chairman: Farhad Mafie, Savant Company Inc.

Panel

Panel:

““Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications”

1:00 - 2:00

EDN

Tensilica

eSilicon

Texas Instruments

Robert Cravotta, Technical Editor, Microprocessors, DSPs, Software, and Tools, EDN Worldwide.

Moderator

Bio: Robert Cravotta currently covers embedded processors, such as microprocessors, microcontrollers, and DSPs, as well as related tools for EDN's audience, providing the latest in technical insight, product updates, and architectural discussions in this vital industry area. Prior to EDN, he work at Boeing and Rockwell where he worked on the control systems for a range of projects including autonomous vehicles and power management for aircraft and the space station. In addition to a BSCSE from UCLA's School of Engineering and Applied Science, Robert has a MS in Engineering Management from California State University (Northridge).
 

1: Steve Leibson, Technology Evangelist.

2: Jack Harding, President, eSilicon.
3: Peter Ehlig, P.E., Fellow DSP, Semiconductor Group, Texas Instruments.
4: TBD
5: TBD

6: TBD

Steve Leibson, Technology Evangelist, Tensilica Corporation.

Panelist


 
Bio: Steve Leibson is an experienced hardware and software design engineer, engineering manager, and design consultant. He spent 10 years working at electronic systems companies including HP’s Desktop Computer Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA workstations) after earning his BSEE cum laude from Case Western Reserve University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of desktop computers and workstations, especially in the areas of system and I/O design.  He then spent 15 years as an award-winning technology journalist, publishing more than 200 articles in Microprocessor Report, EDN, EE Times, Electronic News, and the Embedded Developers Journal. He served as Editor in Chief of both EDN and the Microprocessor Report and was the founding Editor in Chief of the Embedded Developers Journal. Leibson has just written and published “Designing SOCs with Configured Cores,” a treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and published “The Handbook of Microcomputer Interfacing,” which was published in English, French, and Dutch, and was used as a university textbook for many years. In 2004, he co-authored “Engineering the Complex SOC” with Tensilica’s president and CEO Chris Rowen, which has also been used as a textbook in university classes. He has also contributed chapters to several other SOC design books since joining Tensilica in 2001.

Jack Harding, Chairman, President and CEO, eSilicon.


Panelist


Bio: Jack Harding brings more than 20 years of executive management experience in the electronics industry to eSilicon. Prior to co-founding eSilicon, he served as president and CEO of Cadence Design Systems; during his tenure, Cadence was the world's largest supplier of electronics design software. Previously, Harding was president and CEO of Cooper & Chyan Technology, which was acquired by Cadence in 1997. Harding also served as Executive Vice President of Zycad Corporation. He began his career with distinction at IBM.

Harding earned his bachelor's degree in Economics and Chemistry from Drew University and has served as Vice Chairman of its Board of Trustees. He is a Senior Fellow at the Institute for Development Strategies for the School of Public and Environmental Affairs at Indiana University. Harding is a member and former Steering Committee member of the Council on Competitiveness, a Washington, D.C. based organization dedicated to the global competitiveness of the U.S.; and a former National Academies' Committee member for Software, Growth and the Future of the U.S. Economy. He is a frequent lecturer on innovation and entrepreneurship, and has served on many boards of public and private companies. He is a member of Board of Directors for RF Micro Devices (RFMD). His most recent appointment was to the 2007 board of directors for the Fabless Semiconductor Association (FSA).

 

Peter Ehlig, P.E., Fellow DSP, Semiconductor Group, Texas Instruments.
 

Panelist


Bio: Peter has worked at Texas Instruments for over 30 years. In this time he has worked in areas varying from operating systems to CPU architecture definition to semiconductor material science. He has inventions involving in Modems, Cell Phones, Hard Disk Drives, Automotive, and Military applications. He believes SOC success involves at least a working understanding of the end customer’s needs and interests all the way down to the semiconductor physics of the device or devices.
 

2:00 - 2:30

Keynote

Intel

Rose Schooler, General Manager of the Performance Products Division in the Embedded and Communications Group, Intel.



Abstract: Following the theme of the 2008 conference, “Innovation in Chip Design,” Schooler will address how System-on-Chip (SoC) technology has evolved from traditional, three-chip solutions and how SoCs eliminate design barriers and increase performance for various compute platforms. Schooler will also discuss power reduction and management techniques at the architectural, design and physical levels for SoCs. The keynote will also look at new usage models enabled by SoC designs and customer benefits, such as decrease in time-to-market, ability to design products using the same board and cost savings. Finally, Schooler will speak to design challenges that led to the development of current SoC products and how these key learnings can be applied as best practices in the engineering field.

Key take-aways for the audience include:
• Realize performance enhancements enabled by modern SoCs
• Understand design challenges that spurred SoC innovation
• Learn case study for SoC designs with scalability for more than one application
• Gain insight into the future of SoC technology and potential applications

Bio: Rose Schooler is general manager of the Performance Products Division in Intel’s Embedded and Communications Group, responsible for the Intel embedded processors that address applications with high performance and MIPs/Watt requirements. The division produces optimized platforms by delivering high performance silicon for wireless, voice, security, router and other communications market segments.

Schooler has been with Intel for 19 years, beginning as an engineer in fabrication plant process and Corporate Quality program management. She has focused on embedded Intel Architecture for the past 10 years. In addition to her work with System-on-Chip technology, Schooler has led developments around Intel’s storage operations and worked with an internal project focused on digital imaging. Schooler graduated from Pennsylvania State University and holds a bachelor's degree in ceramic science and engineering.
 

2:30 ‒ 3:00

Tensilica

Steve Leibson, Technology Evangelist, Tensilica Corporation.

"Convenient Concurrency Rules Multicore SOC Design."



Abstract: The former lords of multiprocessing in the supercomputing realm call problems that are easily decomposed for distribution to multiple processors “embarrassingly parallel,” as though you should be embarrassed when you need not break your back to solve a problem. Well-known problems such as graphics and network packet processing exhibit this type of parallelism. However, even embarrassingly parallel problems can require some pretty elegant solutions. Fortunately, there’s a lot more parallelism around than is implied in the term “embarrassingly parallel.” In fact, my colleague Grant Martin, Tensilica’s Chief Scientist, coined a new term to describe this situation: “conveniently concurrent.” Conveniently concurrent problems surround us. Even problems formerly considered embarrassingly parallel are conveniently concurrent. Many SOCs destined for high-volume consumer products exhibit plenty of convenient concurrency. Intel and AMD are both pushing multicore processors in the PC space these days. They must because the clock-rate wars have ended due to excessive power dissipation. The same is happening in the world of SOC design. In the PC space, all of the old rules from supercomputing days are seeping in and people are searching for compilers that will decompose big problems into processor-sized chunks. We are much more fortunate in the embedded world. Abundant concurrency is arranged so that the problem naturally decomposes into several processor-sized chunks. This talk will discuss just how conveniently convenient this situation is and how these factors influence multicore SOC design.

Bio: Steve Leibson is an experienced hardware and software design engineer, engineering manager, and design consultant. He spent 10 years working at electronic systems companies including HP’s Desktop Computer Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA workstations) after earning his BSEE cum laude from Case Western Reserve University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of desktop computers and workstations, especially in the areas of system and I/O design.  He then spent 15 years as an award-winning technology journalist, publishing more than 200 articles in Microprocessor Report, EDN, EE Times, Electronic News, and the Embedded Developers Journal. He served as Editor in Chief of both EDN and the Microprocessor Report and was the founding Editor in Chief of the Embedded Developers Journal. Leibson has just written and published “Designing SOCs with Configured Cores,” a treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and published “The Handbook of Microcomputer Interfacing,” which was published in English, French, and Dutch, and was used as a university textbook for many years. In 2004, he co-authored “Engineering the Complex SOC” with Tensilica’s president and CEO Chris Rowen, which has also been used as a textbook in university classes. He has also contributed chapters to several other SOC design books since joining Tensilica in 2001.

3:00 ‒ 3:30

Toshiba

Hideki Takeda, Senior Specialist, Center for Semiconductor Research & Development Semiconductor Company Toshiba Corporation.

"Venezia, a New Scalable Multicore Processor for Mobile Multimedia Applications."

Abstract: Toshiba will introduce a new scalable multi-core processor, Venezia, for the mobile multimedia systems. Venezia is organized by small and low-power processors that are configured by Toshiba’s configurable processor MeP (Media embedded Processor). By changing number of processors and size of caches, it can cover a broad range of applications from low-end to high-end. Furthermore, Venezia’s software platform enables the binary level software compatibility and performance scalability among variety of designs based on Venezia architecture by exploiting coarse-grain thread level parallelism.
 

Bio:
Hideki Takeda received the B.S. degree in Electrical Engineering
and M.S. degree in Electronic Engineering from the University of
Tokyo, Tokyo, Japan in 1992, 1994, respectively. In 1994, he
joined Toshiba Corporation, where he has been engaged in the
development of MPEG-2/H.264 decoder LSIs, media processors. He is
currently involved in the development of video codec LSI for mobile
multimedia system.

3:30 ‒ 4:00

National Taiwan University

Professor Sao-Jie Chen, National Taiwan University
 

"DESIGN OF A VLIW/SMT/DUAL-CORE SWP-SIMD PLX2 PROCESSOR."

Abstract: In embedded multimedia systems, increasing operations per cycle and reducing clock frequency in a design are the key concepts to reduce its energy consumption. Subword-parallel Single-Instruction Multiple-Data (SWP-SIMD) processor provides a low-cost high-performance solution for multimedia applications. But there still exist some critical sequential algorithms that could not be improved by SWP-SIMD. Using VLIW to increase Instruction-Level parallelism (ILP) or simultaneous multi-threading (SMT) to hide memory latency is useful for these algorithms. Our newly designed 64-bit SWP-SIMD core can be partitioned into two 32-bit scalar ALUs, working as a two-issue VLIW core or a dual-core. This multi-mode parallelization capability allows more performance improvement with little hardware cost increase.

Bio: Sao-Jie Chen received the B.S. and M.S. degrees in electrical engineering from the National Taiwan University, Taipei, Taiwan, ROC, in 1977 and 1982 respectively, and the Ph.D. degree in electrical engineering from the Southern Methodist University, Dallas, USA, in 1988. Since 1982, he has been a member of the faculty in the Department of Electrical Engineering, National Taiwan University, where he is currently a full professor. During the fall of 1999, he was a visiting professor in the Department of Computer Science and Engineering, University of California, San Diego, USA. During the fall of 2003, he held an academic visitor position in the Department of System Level Design, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA. During the falls of 2004, 2005, 2006, and 2007, he was a visiting professor in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA. His current research interests include: VLSI physical design, SOC hardware/software co-design, and Wireless LAN and Bluetooth IC design. Dr. Chen is a member of the Chinese Institute of Engineers, the Chinese Institute of Electrical Engineering, the Institute of Taiwanese IC Design, the Association for Computing Machinery, a senior member of the IEEE Circuits and Systems and the IEEE Computer Societies.
 

 4:00 - 4:15

Afternoon Break

Afternoon Break

4:15 - 4:45

Texas Instruments

Dr. Thanh Tran, Embedded Hardware Systems Manager,  Texas Instruments, Inc.

4:45 - 5:15

UCI

Dr. Nader Bagherzadeh, University of California, Irvine.

"General Purpose Processors (GP) vs. Application Specific Processors (ASP), what is the future for multicore designs with 1000's of IPs?"

 

Abstract: In this talk first a brief overview of multicore architectures is discussed. Next, the critical issue of homogeneous versus heterogeneous processing nodes for the future multicore architectures is analyzed, and areas that require further research and development are identified. Finally. concluding remarks are made regarding future designs.
 

Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor.   Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing.  His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications.  The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing.  DARPA and NSF fund the MorphoSys project (total support $1.5 million).  Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine.  Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS).  Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin.  As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms.  He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years.  He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.

5:15 ‒ 5:45

MIPS Technologies

Gideon Intrater, Vice President of Solutions Architecture, MIPS Technologies, Inc.

"Boosting System Performance with Multithreaded Multiprocessing."

Abstract: Today’s SMP operating systems and coherent multi-core platforms offer developers a performance migration roadmap under one OS and the potential to make better use of system resources—maximizing SoC performance on mainstream silicon processes and clock speeds. Adding multithreading on top of a coherent multi-core architecture extracts even more performance by optimizing pipeline utilization in each CPU for minimal additional silicon cost. The performance boost comes essentially for “free” in both hardware and software, since the additional hardware threads are minimal in size relative to a typical SoC design, and multithreading uses the same SMP OS and software programming models as coherent multi-core platforms. In some applications, multithreading can reduce the need for additional processors, or may help achieve an application performance target at lower frequency and/or a smaller synthesized design. This presentation will discuss real-world applications of MIPS Technologies’ MIPS32® 1004K™ coherent processing system—the industry’s first embedded multithreaded, multiprocessor licensable IP core—including the latest performance benchmarking data.

Bio:  Gideon Intrater brings more than 20 years of experience in the semiconductor market to his role as Vice President of Solutions Architecture at MIPS Technologies. Prior to joining MIPS Technologies, Mr. Intrater spent 10 years in technical management positions with National Semiconductor Corporation, where he was most recently director of the Core Technologies Unit. Mr. Intrater earned BSEE and MSEE degrees from the Technion, Israel Institute of Technology, and an MBA from San Jose State University. He holds more than 20 patents. 

5:45 - 6:15

ST Microelectronics

Antonio-Marcello Coppola, Head of the Grenoble Research Laboratory, ST Microelectronics.
 

"Is the "true NoC" just an urban engineering legend?"



Abstract: Recently, most major PC industries as well as embedded devices are shifting to multiple cores (Multicore) on a single chip to improve processor performance. This presentation will discuss the evolution of Multicore for mobile consumer applications from a different angle. It will show the importance that an on-chip communication network is playing during this evolution and trying to see if future Multicore architectures will include or not a true NoC.


Bio: Marcello Coppola is working for STmicroelectronics, he is Head of the Grenoble Research Laboratory within “Advanced System Technology”, a corporate research organization in ST. He studied computer science at Pisa University. In 1992, he received his Laurea degree and started working at the Transputer architecture group of INMOS, Bristol (UK). For 2 and half years he worked on a research program regarding the architecture of the C104 router.
His research interests include several aspects of design technologies for System on Chip, with particular emphasis to Network on Chip, MPSoC architecture, Programming Modeling and system level design. His publication record covers publications in the filed of simulation, modeling, SoC architecture and on-chip communication network. He wrote chapters for different books. He was one the members for the OSCI language working group. He contributed to SystemC2.0 language definition and OSCI standardization. He has chaired international conferences on SoC design and helped to organize several others. He is program committee member of DATE, FDL, CODES+ISSS, DAC. He is cited in Marquis “Who’s Who in Engineering” and IBC biographies.

4:30 pm - 8:30 pm

Exhibit

Conference Exhibit & Reception Open

8:00 - 8:15

Farhad Mafie, President and CEO of Savant Company Inc.

"Welcome and Opening Remarks, Technology/Market Trends."

Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models.

Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis.  He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company.  Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.  His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies. Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

8:15 am - 12:00 am

Innovative Embedded Memory Solutions for Complex Multicore SoCs

Track Chairman: Dr. Nader Bagherzadeh, University of California, Irvine.

8:15 - 8:45

GENUSION

Moriyoshi Nakashima, President, GENUSION.
 

"NVM Technologies - B4-Flash with its Embedded Application and eCFlash (Logic NVM IP)"
 

Abstract:  In the recent non-volatile memory (NVM) arena, NVM technology has been expanding the applications of data storage with NAND Flash. On the other hand other types of NVM applications have been generated in SoC, MCU and all kind of LSI devices by embedded NVM technologies for built-in program storage, security or tuning data. In consequence, many types of memory technologies have been proposed to meet with and to be optimized for individual customer requirements regarding application, cost, density, performance, and so on. It seems to be diverging of NVM technologies in the embedded NVM arena. GENUSION proposes a novel NVM technology “B4-Flash” for code storage which achieves higher performance and reliability with lower cost in comparison with conventional NOR. We propose the embedded NVM IP portfolio to apply wide range of customer requirements with our embedded NVM technology platform of B4-Flash and another GENUSION proprietary NVM of eCFlash as logic NVM.

Bio: Moriyoshi Nakashima joined Mitsubishi Electric Corporation in 1981. He had been in charge of non-volatile memory process integration and technology development including embedded NVM applications until 1998. He became the manager of flash memory business unit in 1998 to start memory solution and multi chip package (MCP) business for mobile phones leading to one billion US dollar business and world biggest MCP share in the application. He quitted Mitsubishi in 2002 and founded GENUSION. He is a president of GENUSION, Inc. developing novel NVM technologies.

8:45 - 9:15

Kilopass Technology

Craig Rawlings, Director of Marketing, Kilopass Technology Inc.

 

"Demystifying Logic NVM Options."

CMOS Logic NVM IP solutions each have advantages and disadvantages that hinge on their respective underlying technologies. In this presentation, an introduction ­will be made for the three types of Logic NVM technologies in production today: fuse, antifuse, and floating gate. Each technology will be described in terms of its capabilities as an embedded NVM technology. Based on each technology analysis will also be provided regarding process trends and the future of CMOS Logic NVM for SoC applications.

Bio: Craig Rawlings has more than 15 years of experience in the semiconductor industry. Prior to joining Kilopass, Craig held management and executive-level positions at Hewlett-Packard, Actel, Resilience, and Progress Software. Kilopass is Craig's fourth early stage start-up experience. Craig's first start-up right out of engineering school was Cericor which was later purchased by HP. He was also part of the initial team at Actel and led that company's business expansion in the US, Japan, and Asia Pacific participating in Actel's subsequent IPO. Craig holds a B.S.E.E. degree and a Masters of Business Administration from Brigham Young University.

9:15 - 9:45

Innovative Silicon

Jeff Mitchell, Director of Technical Marketing, Innovative Silicon.

"Z-RAM: A Better DRAM."
 

Abstract: After nearly 40 years of evolution, the classical 1T/1C DRAM is finally reaching its scaling limit. As a possible replacement technology, Floating-Body Memory is getting increasing industry attention. Z-RAM is a type of Floating-Body Memory which uses a novel method of reading and writing to the memory cell utilizing the bipolar device intrinsic to the MOS transistor. Taking advantage of this "bipolar operating mode" of a Floating-Body Memory increases the operating margins of the memory cell. This substantially improves its manufacturability and creates, for the first time, a truly viable candidate for replacement of the 1T/1C DRAM.

Bio:  Jeff Mitchell is Director of Technical Marketing at Innovative Silicon. He has more than 20 years of experience in the electronics industry and has been awarded several patents. He has had a varied career, holding positions in engineering, marketing, and business development. Mitchell has a B.S. in Engineering from Harvey Mudd College.
 

9:45 - 10:00

Morning Break

Morning Break

10:00 - 10:30

Keynote

Georgia Institute of Technology

Professor Rao R. Tummala, Director of Microsystems Packaging Research Center. Georgia Institute of Technology.

"An All Silicon 3D Systems Technology, An Emerging and Disruptive Technology for Convergence of IC, Package and System," 
 

Abstract: 3DASSM is an all Silicon System using Si for ICs, components, packages and system boards using 3D technologies. It is an ultra-miniaturized, ultra-functional, and low cost systems technology, enabled by new designs, thin-film materials, large-area low-cost processes, and heterogeneous functional integration leading to lower cost convergent system products. Such a technology is presented as achieving better electrical performance, ultra-miniaturization, greater heterogeneous integration, higher thermal performance and higher thermo-mechanical reliability at lower-than-today's organic-based hybrid packages and systems.

This technology is proposed as an R&D industry consortium in partnership with Fraunhofer (Germany) and KAIST (Korea) and includes exploratory interdisciplinary fundamental research in design and test, Si package replacing organic package, low cost TSV and stack bonding, thin-film embedded active and passive components, and system interconnections. In addition, the consortium integrates the above fundamental research into useful test vehicles to demonstrate the commercial feasibility of cost effective 3D structures, silicon packages, and all silicon modules with seamless integration of ICs with their FEOL and BEOL, as well as with package wiring. More than 20 projects are proposed in these areas.  3DASSM differs from other 3D industry programs in a variety of ways, such as:

1. 3DASSM starts with the current industry problem, the high cost and low reliability of TSV and stack bonding. Here we propose several fundamental research projects to address cost and reliability, such as new fabrication methods for low cost and high density TSVs, new structures that improve the rmomechanical reliability, novel low cost solder and adhesive stack bonding methods. In addition, this research will culminate in a 3D stack bonding test vehicle and a Si package test vehicle to demonstrate the improved performance, reliability, and manufacturability of the technologies developed.
 

2. 3DASSM goes beyond current 3D programs to demonstrate a double-sided silicon package replacing the organic package enabled by low cost TSV in a seamless integration. This test vehicle will address shortcomings of the organic package such as wiring and I/Os, thermal performance, warpage and cost.
 

3. 3DASSM leads to next generation of wafer level packaging. This is referred to as Wafer System module in the 3DASSM. In this approach, ICs with both FEOL and BEOL are integrated with seamless integration of package wiring and cost effective thin embedded components on both sides of wafer enabled by TSV
and 3D interconnections.

The ultimate goal is to design, demonstrate and commercialize a highly integrated all silicon system module (ASSM). 3DASSM, therefore, is a global Industry-Academia consortium on a global topic with potential to
become a disruptive and revolutionary silicon module technology in the near term and a systems technology in the long term.

Bio: r. Rao Tummala received the BE degree in Metallurgical Engineering from the Indian Institute of Science, Bangalore, India and the Ph.D. degree in Materials Science and  Engineering from the University of Illinois. He joined the faculty at Georgia Tech in 1993 as a Pettit Chair Professor in Electronics Packaging and as Georgia State Research Scholar. He is also the Director of the Microelectronic Systems Electronic Packaging Research Center funded by NSF as one of its Engineering Research Centers, the state of Georgia, and US electronics industry. Prior to joining Georgia Tech, he was an IBM  Fellow at the IBM Corporation, where he invented a number of major technologies for IBM's products for displaying, printing, magnetic storage and multichip packaging for  which he received 16 Technical, Outstanding and Corporate Awards from IBM. He is both a fellow of IEEE and the American Ceramic Society, a member of the National Academy of Engineering, 1996 President of IMAPS and current president of the IEEE-CPMT Society. He was recently named by Industry Week as one of the 50 Stars in the US, for improving US competitiveness. He is co-editor of four widely-used Microelectronics Packaging Handbooks. He published 205 technical  papers and holds 68 US patents and inventions. He has received many awards: David Sarnoff, sustained technical achievement award from IEEE, John Wagnon's award from IMAPS, Materials Engineering achievements award from ASM-I, Distinguished Alumni Honor award from University of Illinois and the Indian Institute of Science, and Arthur Friedberg Memorial award and the John Jeppson Award from American Ceramic Society, the Total Excellence in Electronics Manufacturing (TEEM) Award from the Society of Manufacturing Engineers, and the European Materials Award from DVM. He recently received the highest faculty award at Georgia Tech, the Distinguished Faculty Award.

10:30 - 11:00

UMC

Dr. Raymond Leung is vice president of memory IP development at UMC.
 

"Embedded Memory IP Challenges."

Abstract: In the modern SoC era, memory becomes an important and essential IP requirement for SoC design. UMC offers state-of-the-art embedded memory solutions to meet a variety of applications. These solutions are available in process technology nodes from 0.35um all the way down to 40nm. This paper will focus on the technical characteristics of each of the embedded memory IP and how a combination of these solutions are needed to realize today’s SoC’s.  High quality embedded non-volatile memory (eFuse, OTP, MTP, EEPROM and eFlash) can be used for trimming, redundancy, data encryption, ID, coding and programming. Additionally, UMC's proprietary URAM's is a good solution for higher memory density requirements. The important features of URAM are smaller form factor, higher bandwidth/speed and lower power consumption than the traditional embedded 6T-SRAM solution. For lower density, SRAM compilers are available for greater flexibility and more choices for port configurations. A general overview of our portfolio will be presented, together with highlights of each of the solutions. A couple of customer SoC examples will also be presented to illustrate general application of our IP’s. All of these enabling IPs have been helping UMC customers to deliver their ICs to market in an effective and timely manner.

Bio: Raymond Leung is vice president of memory IP development at UMC and has over 20 years of semiconductor industry experience prior to joining the company in 2006. Before that, he was the executive vice president at Celestial Semiconductor and he served as vice president of engineering at Virage Logic, where he was responsible for developing the foundry libraries and managing most of the remote development operations from 1998 to 2004. Other companies benefiting from his expertise include LSI Logic Corp (1989-98) where he served as senior director, and prior to that Philips Semiconductor (1982-89) where he was a senior design engineer in the PLD division. He earned his BSEE degree at Columbia University in 1981, and his MSEE degree at Stanford University in 1982.

11:00  - 11:30

Virage Logic

Luigi Ternullo, Product Marketing Manager, STAR Memory System, Virage Logic Corporation
 

"Using Data Traffic Efficiency Metrics to Select the
Best DDR Memory Controller for your Design."
 

Abstract: The use of DRAM has become a key architecture consideration for many System-on-Chip (SoC) designs. Whether the DRAM is designed to be on-chip (embedded DRAM), or an off-chip DRAM subsystem, the SoC will very likely require an on-chip memory controller, and many times an IP-based memory controller is used.  Understanding how to select the best IP-based memory controller for specific applications can be a complex task. Some of the obvious criteria, such as performance, area, cost, power, and latency all need to be factored in, however, using a data traffic “efficiency” metric (bandwidth delivery/theoretical maximum bandwidth) has proven to be the most important criteria for a wide range of applications. This paper will describe the efficiency metric and will show measurements for typical efficiency levels that can be achieved for different memory controller architectures. This will make it easier to determine where in the efficiency spectrum a particular memory controller design resides. Additionally, we will use two examples from real systems (a networking router and an image processor for a security application), to demonstrate how efficiency can be used to make system tradeoffs that can result in significant savings, lower system cost, lower power consumption, gain higher system performance, and quicker time-to-market.

Bio: Luigi Ternullo serves as Product Marketing Manager for Virage Logic’s Application Specific IP product solutions such as Double Data Rate (DDR) memory controllers. Prior to joining Virage Logic in 2006, Ternullo held technical marketing management positions and senior engineering management positions at Agere, Vanguard International Semiconductor, and IBM. His range of experience includes SRAM design, memory and logic built-in self-test (MBIST and LBIST). Mr. Ternullo also holds over 25 patents in BIST and memory design, and has authored several BIST papers. He holds a B.S. and M.S. in Electrical Engineering from Rochester Institute of Technology, and M.B.A. from Lehigh University.
 

11:30 - 12:00

Novelics

Dr. Gil Winograd, Chief Operating Officer & Co-Founder, Novelics Corporation.
 

"Innovative Embedded Memories."

Bio: Prior to co-founding Novelics, Gil Winograd was a Principal Scientist at Broadcom Corporation responsible for the design of leading-edge memories, high speed full-custom circuits, and compiler and software automation processes for custom circuits. Dr. Winograd brings to Novelics a diverse background of software design, IC design, and device physics and fabrication. Dr. Winograd received his BSEE from the University of Illinois, Champaign in 1991, his MSEE from the University of Illinois in 1994 in Computer Engineering, and his Ph.D. from Stanford University in 2000, specializing in lithography. He has six technical publications and more than 30 patents issued or pending.