6th International SoC Conference - Savant Company Inc.

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5th International System-on-Chip (SoC) Conference, Exhibit & Workshops

November 7 & 8, 2007 — Radisson Hotel Newport Beach, Southern California

Keynotes & Panels

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Keynote Speakers

Intel
Dr. Jeff Parkhurst
Academic Research Programs Manager in the Design Sciences Area.

National Semiconductor
Dr. Ahmad Bahai
National Fellow and Chief Technology Officer, NS Labs. Adjunct Professor,
Stanford University, UC Berkeley.

Carnegie Mellon University

Dr. Rob Rutenbar

Professor of Electrical & Computer Engineering,

Director of the National FCRP Focus Center for Circuit & System Solutions.

Jazz Semiconductor
Dr. Marco Racanelli
Vice President of Technology & Engineering.

Three Enlightening & Informative Panels

"Emerging Wireless Chips: The Development & Integration Challenges"

Moderator: Glen Gibbons, Inside GNSS, Editor and Managing Partner

"Emerging Trends for Complex SoCs: From Advanced Multicore/CPUs/DSPs to Innovative Embedded Memories"

Moderator: Maury Wright, Editorial Director, EDN Worldwide

"Structured ASICs: Dead or Alive"

Moderator: Steve Leibson, Contributing Editor, EDN

See Steve's Notes

Panelists:

1: Bruce Peetz, Vice President of Advanced Technologies, Trimble.
2: Charles Abraham, Director of Engineering for the GPS Business Unit of Broadcom, Corporation.
3: Sanjai Kohli, Chief Technical Officer, SiRF Technology.
4: Cormac Conroy, VP Engineering, Qualcomm
5: Clint Powell, Chief Architect and Global Platform Systems and Architecture Manager, WCO, Freescale.

Panelists:

1: Dr. Cyrus Afghahi, CEO, Novelics.
2: Mike Uhler, Chief Technology Officer, MIPS Technologies.
3: Jonah Alben, Vice President of GPU Engineering, NVIDIA.
4: Jeff Bier, Co-Founder and President, Berkeley Design Technology.
5: Grant Martin, Chief Scientist, Tensilica.

Panelists:

1: Soheila Lighvani, Director, Design Engineering, Western Area Design Center, Toshiba America Electronic Components.
2: Jasbinder Bhoot, Senior Director, Marketing, eASIC Corporation.
3: Sunil Baliga, VP & GM, Custom Silicon Business, InSilica.
4: Paul Hollingworth, Senior Director of the HardCopy Product Group, Altera.
5: Phillip LoPresti, CEO & President, Kenet Inc.
6: Chris Moezzi, Vice President of Business Development, Faraday Technology.

By Steve Leibson, Contributing Editor, EDN:

Structured ASICs offer system designers many advantages. Measured against standard-cell ASICs, structured ASICs promise lower mask costs and faster turnaround times. Measured against FPGAs, they promise lower part costs, lower power dissipation, and lower energy consumption. Structured ASICs should have found a comfortable place in the system-designer’s toolkit given these tangible advantages. They didn’t. Companies that were early advocates of the concept have dropped their products or gone out of business and few others have entered the fray. Although structured ASICs have succeeded in some cases, their future as broadly viable design alternatives to ASICs and FPGAs still remains very much in question. The question is: What went astray and why?

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