5th International SoC Conference

98% of attendees at the Savant Company Inc. International SoC Conference and Exhibit said they would recommend this SoC Conference to someone else! Please See Client Testimonials

International System-on-Chip (SoC) Conferences
Technical Advisory Board

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Keynote Speakers

Intel

Dr. Jeff Parkhurst

Academic Research Programs Manager in the Design Sciences Area.

National Semiconductor

Dr. Ahmad Bahai

National Fellow and Chief Technology Officer, NS Labs. Adjunct Professor
Stanford University, UC Berkeley.

Jazz Semiconductor

Dr. Marco Racanelli
Vice President of Technology & Engineering.

Platinum Sponsors

Gold Sponsors

Orange County Chapter

Technology & Media Sponsors

Orange County Chapter

Selected Participating Companies & Organizations

Call For Sponsors, Speakers & Exhibitors

For Speaking opportunities, conference sponsorship and exhibitor opportunities (tabletop exhibits), please contact:

SoC@savantcompany.com or (949) 851-1714

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The Savant SoC Conference Organizing Committee is pleased to announce the Call for Presenters for The 5th International System-on-Chip (SoC) Conference in Southern California.

Track & Session presenters, Keynote Speakers, and Panel Members who can contribute their professional expertise have a wonderful opportunity to share their innovative SoC technology or their products at this event with a very focused and targeted audience.

Presenters and Keynote Speakers will be considered for leading-edge topics such as:

CMOS, Scaling, and the Future
Analog Integration in Complex SoCs
Analog IPs
Interconnect-Centric SoC Design
Network-on-Chip (NoC)
Imaging System- on-Chip (I-SoC) -- CMOS Image Sensors & Image Processing
Video Compression IPs for H.264, MPEG-4, VC-1, Wavelets, JPEG2000
Video-related IPs such as DVB-H, DMB, ISDB-T, DVB-T, HDTV, etc.
Wireless IPs for GPRS, HSPDA, 3.5G, 4G, 802.11n, 802.15.3a (UWB), 802.16 (WiMax), SDR (Software Defined Radio), etc.
ASIC/SoC/Foundry for 65nm and Sub-65nm
SoC Design Challenges
Is Structured ASIC Dead?
Analog Design Challenges
FPGA Technology Beyond 90nm
High-speed IOs (SerDes, etc.) Design Challenges
1394, USB, and other high-speed IO IPs
Modeling Techniques for SoC/ASIC Designs
Configurable CPUs and DSPs for SoC Platform Design
SIP vs. SoC vs. 3D Packaging
SoC Design Using Programmable ICs & Structured ASICs
System-on-Chip Platform Design
Distributed processing on One Die
EDA Tools for 45nm and Post-45nm
Memory Subsystem Design
Memory on-chip vs. off-chip
New Memory Technologies
New Ideas in Placement and Floorplanning
New Opportunities in High-level Synthesis
ASIC/SoC Design Methodologies
IP Design, Modeling, and Reuse
SoC Testing and Verification
... and other topics

Panel Moderators and Panel Members will be considered for topics such as:

Analog Integration and Design Challenges
Configurable CPUs and DSPs for SoC Platform Design
IP Design, Modeling, and Reuse
EDA Tools for 45nm and Post-45nm
FPGA vs. ASIC vs. SoC
Memory Subsystems for Complex SoCs
Innovative Approaches for Low Power Designs
SoC Testing and Verification

Presentation Proposals (or) Presentation Abstracts:

(Please be sure to include a short bio and your photo with your proposal.)

SoC Conference Organizing Committee continues to consider presentation proposals/abstracts for various topics. To take advantage of this outstanding opportunity, please send your presentation proposal or abstract to: Savant SoC Conference Organizing Committee at SoC@SavantCompany.com ASAP.