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Platinum Sponsors
Gold Sponsor
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4th
International System-on-Chip (SoC)
Conference & exhibit
Detailed Program Information (Abstracts & Bios) for wednesday, November 1, 2006* |

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8:00 am - 8:15 am |
Farhad
Mafie, President and CEO of Savant Company Inc.
"Welcome and Opening Remarks, Technology/Market Trends."
Farhad
has over 20
years of experience in semiconductor and computer businesses and more than 10
years of university-level teaching experience. Farhad is the former
Vice President of Marketing/Business Development and Technical Sales Engineering at
Toshiba America Electronic Components, Inc. He was responsible for marketing
the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth,
Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).
He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer
products & solutions based on ASSP and SoC Models.
Farhad established Toshiba's on-line
Tech-Support System as well as Toshiba's on-line System Solution Selling
methodologies for all Toshiba's products in the North American markets.
These on-line systems were adopted by Toshiba on a worldwide basis. He
also developed Toshiba's ASSP Business Unit and Technical Sales Engineering
Team as two brand new organizations for the company.
Farhad has also worked at Lucent Technologies
on marketing communications ICs,
Toshiba Information Systems on product definition for Toshiba's notebooks
and handheld products, Unisys on designing new processors and computer
systems, and MSI Data on
designing data collection products. He has a Master of Science and a
Bachelor of Science degree in Electronic Engineering from California State
University, Fullerton.
His combined business and academic experience has
given Farhad a unique ability to effectively communicate complex new
technologies to business professionals at all levels, as well as the ability to
foresee emerging leading-edge technologies.
Farhad is an author and a
translator, and he writes articles for a variety of journals and Web-based
magazines on technology and political affairs.
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8:15 am - 12:00 am |
New CPU and DSP Cores for
Complex SoC
Applications
Track Chairman: Shay
Gal-On, EEMBC Director of Software Engineering & Leader of EEMBC Technology
Center
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Shay
Gal-On, EEMBC Director of Software Engineering & Leader of EEMBC Technology
Center.
"Track Chairman"
Shay Gal-On is EEMBC’s Director of Software Engineering and
leader of the EEMBC Technology Center. Previous to joining EEMBC, he was
Principal Performance Analyst in the Microprocessor Products Group at PMC
Sierra, and his career has also included roles as a software engineer for
Improv Systems and Intel.. A compiler/tools expert, he has devoted
considerable effort to analyzing the effects of various compilers on
benchmark performance and has ported the EEMBC benchmarks using Wind River
Diab, Green Hills MULTI, ARM.RVDS, Improv Jazz tools, the Stretch/Tensilica
development environment, and many versions of gcc. He has also served as a
member representative on the EEMBC Board of Directors and thus is well
acquainted with EEMBC processes, having ported and optimized the benchmarks
for a wide variety of architectures.
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Dr.
Gheorghe Stefan, Chief Scientist & Co-Founder, Connex Technology, Inc.
"The
CA1024 :SoC with Integral Parallel Architecture for HDTV Processing"
The CA1024 SoC is the commercial implementation of an
Integral Parallel Architecture, centered on ConnexArrayTM (a massively
data-parallel processor), a time-parallel speculative array, and a
Multi-Threaded host engine (MTH), providing the programmable media processor
architecture developed by Connex Technology, Inc. The chip is described and
its performances in the video decoding domain are presented. Why an
Integral Parallel Architecture? Because digital video work loads (as
almost any complex real application) exhibit significant data parallel
block-transform-based computation in combination with inherently serial
recursive entropy coding/decoding workloads. Accordingly, the system must be
optimized for vector processing and stream processing, as fully programmable
resources for data parallel and speculative time parallel computing,
respectively. More, the real time application in HDTV consists in few
distinct functional threads such as stream demultiplexing, audio and video.
Data Parallel Resources: ConnexArray™ (CA) is a linear array processor
comprised of 1024 simple and small processing elements (PEs). Two stack
processors control the CA: Instruction Sequencer (IS) and Input/Output
Controller (IOC). The IS issues one instruction for all PEs in each cycle.
The instruction is executed by each PE according to its internal state. In
parallel, the IOC controls the transfer of vectors between CA and the
external memory. At 200 MHz, CA provides 200 GOPS (>40 GOP/Watt), 400 GB/sec
internal bandwidth, and 3.2 GB/sec external bandwidth. Time Parallel
Resources: Speculative Accelerator is an optimized engine for the
intrinsically serial entropy coding or decoding algorithms associated with
advanced video compression & decompression. It is a MIMD array of eight
elements capable of processing in real time two H264 HD video streams.
How CA1024 is Programmed: The Connex Programming Language (CPL) is
based on the familiar C/C++ syntax. It hides the complexities of the
parallel execution hardware. The first version of CPL addresses the needs of
video applications by providing support for operations on vectors made up of
16-bit components (integer and fixed-point). An I/O library provides a
number of functions that are optimized for video applications. All calls are
non-blocking (i.e. asynchronous), because they are run on IOC strictly in
parallel with CA/IS code. : CA1024 performance for video-centric
algorithms. Our performance analysis predict that with the dual HDTV
codec H.264 or VC1 advance video decode, the CA1024 has ample headroom to
inject error resiliency, color management, scaling and de-interlace
processing. For some basic functions involved in HDTV processing we have:
Pixel-based motion detection: 0.04 clock cycles / pixel or 2400 FPS. 8x8
IDCT: 5 clock cycles / block. SAD: 1.25 clock cycles / block 16x16
Gheorghe Stefan, PhD, Chief Scientist & co-Founder, Gheorghe Stefan
has over 30 years of experience in teaching, research and industry roles
including digital design and computer architecture. He has developed the
architectural and structural design and basic algorithms of the
ConnexArrayTM architecture. Prior to found Connex Technology, he designed
and implemented a version of the Lisp Machine, initiated the design of
ConnexArrayTM, and authored more than 15 books and 100 articles on digital
design & computer architecture. He is also teaching at the Politehnica
University of Bucharest, Romania where he serves as a tenured professor in
electronics and computer engineering and received his PhD in electronics.
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Mike
Butts, Architect, Ambric, Inc.
"Implementing
A New, Massively-Parallel, MIMD Computing Fabric SoC "
Ambric has developed the first globally-asynchronous, scalable,
software-programmable teraOPS IC platform. Ambric has also solved the
programming challenge of developing and testing general-purpose
massively-parallel, MIMD applications. Ambric’s architecture offers a
significant price-performance advantage over high-end DSPs and FPGAs, and
can keep pace with the exponential growth of Moore’s law.
Mike Butts: Butts came to Ambric from another programmable IC platform
company that he co-founded. He has a rich background in architecting
large-scale reconfigurable hardware. In the 1980s, he co-invented hardware
logic emulation using reconfigurable hardware -- technology that has
developed into a $100 million per year market. Butts developed a number of
reconfigurable chips and system products in his twenty-year career in the
electronic design automation industry, including stints at Mentor Graphics
Corporation, Quickturn Design Systems, Synopsys, Inc., and Cadence Design
Systems, where he was a Cadence Fellow. Butts' roots are in advanced
computer architecture, which he further developed while at Floating Point
Systems, Beaverton, Ore. He holds a B.S. and an M.S. in Electrical
Engineering and Computer Science from M.I.T.
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Steve
Steele, Director of Business Development, Data Engines, ARM Ltd
"Delivering
Data Engine Benefits in the System Context."
Over recent years, there has been a steady progression
towards design platforms that enable high-performance, feature-rich products
to be introduced to the market in rapid succession. As companies seek to
further differentiate their products, they require higher levels of audio,
image and video quality to be incorporated within the latest designs and are
turning to specialized DSP solutions to fulfill their needs.
ARM Data Engines are increasingly being integrated into SoCs to provide the
necessary specialised data processing that delivers an optimal balance of
high performance, low power consumption and less area (better PPA). Data
Engine designs, based on ARM's proprietary OptimoDE technology, are
available across a wide range of applications.
Because system integration occurs towards the end of the design process, it
is most important that process runs smoothly; the cost of schedule delays
can be immense. ARM seeks to provide technologies that provide a
comprehensive solution for integrating its data engines in a systematic and
system-programmable way into the SoC. It is essential that the compelling
PPA benefits of data engine technology are preserved when integrated within
the SoC and when programmed at the system-level.
An example of ARM's data engine technology is AudioDE(tm), an application
class-specific data engine that is tailored for embedded Digital Signal
Processing (DSP) in portable audio applications. The combination of
architectural properties and the highly parallelizing compiler yield a
solution that results in minimal power and area requirements for audio
applications. The AudioDE product connects into ARM's broad ecosystem of
simulation, modeling, debugging, software and hardware to provide for
efficient, seamless integration.
ARM will discuss the company's approach to implementing such domain-specific
applications into today's consumer devices and how the company is delivering
optimized performance levels of dedicated logic with re-programmability of
general purpose DSP solutions.
Steve Steele joined ARM in 2001, initially working as a program manager for
Java. Steve then moved on to managed a team looking after ARM's software
business that included Java, power management and security products. More
recently, Steve moved over to ARM's Data Engines Division to drive business
development. Before joining ARM, Steve worked at Thales Optronics
where he managed the design and build of a new EO reconnaissance system for
the Royal Air Force. Prior to that, Steve worked at Vinten where he worked
on embedded hardware and software design, system design and product
marketing in the broadcast television industry. Steve holds a BSc (Hons)
in Physics with Physical Electronics from the University of Bath, and an MBA
from Nottingham Business School.
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9:45 am - 10:00 am
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Coffee Break |
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10:00 am- 10:30 am
Keynote |
Arup
Gupta, Director, Wireless Platform Technology at Mobility Group, Intel
"Advances
in packaging, CMOS design and flexible architectures for new ultra-mobile PC
(UMPC)"
Dr. Dominik Schmidt,
Intel
Wireless
technology has been evolving across various vectors from cellular networks
to wireless short range personal area networks to wireless broadband
networks. As we move to the third decade of commercial wireless technology
deployment, there is a growing trend for a multitude of these technologies
emerging on individual client platforms. Network providers are looking for
the best possible connection with lowest cost per bit of data services;
consumers are looking for client platforms that work together to bring
unique services not possible with single networks at an affordable price.
This talk will focus on new technologies for multi mode client devices, and
how these technologies can extend the service providers revenue model. The
goal is keeping cost of delivery of services low while providing new
applications for the emerging class of client platforms.
Wireless technology is becoming pervasive, with several new standards being
added to the mobile device paradigm. While single-protocol solutions still
dominate, portable, multi-mode wireless is already here. For example, Intel
has introduced a new ultra-mobile PC (UMPC) for Windows with up to five
simultaneous wireless standards. The success of these solutions will be
dictated by their low cost, small size and minimal power consumption. This
talk will focus on the technology advances in packaging, CMOS design and
flexible architectures necessary to achieve these difficult targets.
Arup Gupta is the Director of the Wireless Platform Technology group
at Intel. Arup joined Intel in late 2002 as the CTO of the newly formed
Consumer Electronics group. Prior to that he was the VP of Engineering at
two startups Morphics Technology and Televersal Systems. Arup was the
Engineering Director at Lucent Technologies leading Silicon and systems
teams for complete reference design platforms in Consumer Wireless and
Bluetooth till 2000. Arup spent over 14 years at AT&T/Lucent Bell Labs in
various design and management positions. During his career he and his team
have produced over 20 commercially successful DSPs, mixed signal and RF ICs.
Arup's interest lies in Architecture for high performance signal processing
and Reconfigurable computing. Arup has a MSEE from Washington State
University and a BTech (Hons) from IIT Kharagpur, India in addition to
several Executive management courses from Harvard University and Wharton
School of Business. He has 3 patents awarded on DSP architectures and
several patents pending. Arup is a Senior member of IEEE and a member of
Sigma Xi.
Dominik Schmidt, M.S.M., Ph.D., PE, has been working in the
semiconductor industry for 17 years. He was at Altera working on
reconfigurable logic and has worked with Sharp, TI, Cypress, and TSMC. He
cofounded Pixel Devices International (PDI) in 1997, one of the first
companies to offer CMOS imaging chips. After PDI was acquired by Agilent, he
founded Airify Communications, specializing in multi-protocol wireless chip
design. After the acquisition of Airify, Schmidt is now at Intel Corporation
leading efforts to design the next generation of advanced wireless products.
He has also worked for the Stanford Linear Accelerator and Lawrence Berkeley
National Laboratory on several advanced projects, and has consulted for
several large companies and startups in the mixed-signal and RF design
areas. He has taught at UC Extension since 2000 and also teaches at Tsinghua
University in Beijing. He is writing a graduate textbook on RF Design for
Elsevier Press.
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Steve
Leibson, Technology Evangelist, Tensilica, Inc.
"Nanometer
MPSOC Design Using Configured Cores"
This presentation emphasizes a processor-centric MPSOC
(multiple-processor SOC) design style consistent with the realities of
21st-century, nanometer silicon. Assignment of on-chip tasks to
firmware-controlled processor cores whenever possible maximizes SOC
flexibility, cuts power dissipation, reduces the size and number of
hand-built logic blocks, shrinks the associated verification effort, and
thus minimizes overall design risk. Microprocessor cores vary widely
in their attributes as do packaged microprocessor ICs for board-level
designs and SOC designers still compare and select processor cores the way
they previously compared and selected packaged microprocessor ICs. This
selection method assumes that the laws of the microprocessor universe have
remained unchanged since Intel introduced the 4004 processor in 1971, but
this assumption is no longer valid. Existing SOC design methods
attempt to match on-chip tasks to a few dissimilar, fixed-ISA processor
types (general-purpose processors and DSPs), which greatly complicates
software development. A family of software-compatible, configurable and
configured microprocessor cores can efficiently implement a wide range of
simple control, conventional DSP, and media-processing tasks while employing
a consistent set of software-development tools so that programmers familiar
with one processor in the family can easily switch to another. This
presentation is based on a new book, “Designing SOCs with Configured Cores,”
which will be published in July, 2006 by Elsevier under its Morgan Kaufmann
imprint.
Steve Leibson is the Technology Evangelist for Tensilica, Inc. He formerly
served as the Vice President of Content and Editor in Chief of the
Microprocessor Report, Editor in Chief of EDN Magazine, and Founding Editor
in Chief of Embedded Developers Journal magazine. He has written hundreds of
articles that have appeared in electronics industry trade magazines
worldwide and he has won many industry awards for his writing. While
at the Microprocessor Report, Leibson developed and presented many
microprocessor seminars and he organized and served as MC for the
Microprocessor and Embedded Processor Forums. He holds a BSEE Cum Laude from
Case Western Reserve University and worked as a design engineer and
engineering manager for leading-edge system-design companies including
Hewlett-Packard and Cadnetix before becoming a journalist. Leibson is an
IEEE Senior Member.
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Dr. Thanh
Tran, Embedded Hardware Systems Manager,
Texas
Instruments, Inc.
“Dual-Cores SOC Simplifies Digital Video Systems”
Texas Instruments’ DaVinci™ technology leverages a tightly
integrated set of multimedia codecs, application programming interfaces
(APIs), frameworks and development tools, all of which are optimized for the
TMS320DM644x system-on-chips (SoC) to simplify innovation for digital video
systems. The foundation of the DaVinci technology’s flexibility comes from
its programmable architecture, with the first processors, the DM644x,
featuring a dual-core ARM plus DSP architecture. This presentation will
include a detailed overview of the architecture that allows for this
flexibility. It will also evaluate how the integrated peripherals such as
video encoder, hardware video accelerators, video port subsystem and audio
interfaces simplify the implementation of digital video systems. Finally, it
will address how the combination of the processors, APIs and the
availability of production-ready codecs simplifies digital video innovation
like never before.
Dr. Thanh Tran has over 21 years of experience in audio, video, computer and
communication systems design and is a Hardware Productization Manager at
Texas Instruments Incorporated. At TI, he is leading a hardware systems team
to develop reference designs and frameworks for high speed SOC systems. He
has held other senior design positions at Compaq Computer, ReplayTV, Eagle
Wireless Incorporated, Bose Corporation and Zenith Electronics Corporation.
Tran is an IEEE Senior member and currently serves on the IEEE
System-On-Chip Organizing Committee and the International Conference in
Consumer Electronics Technical Program Committee. He has published over 14
technical papers and holds 18 issued patents related to designs of computer,
video, audio and communication systems. Tran’s doctoral research, gated
direct sequence spread spectrum clock distribution system, led to three
patents pending and a startup company, X-EMI, in Texas. He is currently an
adjunct faculty member at Rice University where he is teaching a graduate
electrical engineering course in digital audio and video systems design.
Tran received a bachelor’s of science in electrical engineering from the
University of Illinois at Urbana-Champaign, Illinois and master’s of
electrical engineering and a doctorate in electrical engineering from the
University of Houston, Houston, Texas.
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George
Szanto, Vice President of Marketing, Silicon Hive
"Hitting
the Sweet Spot Between Hard Wired Logic and Programmable DSPs With HiveFlex
Processors"
SoC platform owners face ever decreasing time to market and
time in market challenges. One solution to this dilemma is the use of
application specific programmable DSPs which replace traditional hardwired
logic. HiveFlex processors, delivered as soft IP, for mobile and fixed
terminals reduce design cycles by up to a factor of 3 while maintaining
performance, power dissipation, and area constraints found in typical high
volume consumer ICs. Specific applications in communications (DTV,
TvonMobile, WiMax/Wibro) and image signal processing (ISP, CMOS sensors)
will be presented along with design data highlighting how such IP hits the
sweet spot of current SoC platform owner’s needs.
As Vice President of Marketing For Silicon Hive George is responsible for
all marketing and partnership activities worldwide. He has over 15 years of
high tech marketing experience in a variety of industries spanning IP sales,
security IC’s and imaging systems. Recently he held senior management
positions with SafeNet and SRC Vision focusing on product management,
business development and product marketing. Prior to that he owned and
operated his own international technology consulting company. George holds a
BA degree in applied physics from University of California San Diego
augmented by business education from University of California Berkeley and
Syracuse University.
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12:00 pm - 1:00 pm |
Lunch |
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1:00 pm- 1:30 pm
Keynote |

Dr. Mehdi
Hatamian, Vice President of Engineering, DSP Microelectronics,
Broadcom
"From
5000nm to 45nm: A 30 Year Journey in Chip Design
Low Power Challenges in System-on-a-Chip Design"
Increasingly
complex system-on-a-chip (SoC) designs have been one of the driving forces
behind the massive adoption of broadband connectivity and, by extension,
Internet technologies. The ability to integrate massive mixed-signal
circuits capable of higher performance and increasing functionality onto
smaller and smaller pieces of silicon has enabled the proliferation of wired
and wireless communications on a widespread scale. Today’s portable devices
are converging into complete single-chip SoCs, adding both complexity and
power challenges for the most talented chip designers. Consequently, the
increasing presence of single-chip components increases the need for greater
power efficiency in subsequent generations of these converging products.
Although advances in silicon process geometries provide some performance
improvements, they also introduce new complications that can impact the
success of an SoC product.
This presentation will examine the challenges and necessities of optimizing
SoC designs for improved low-power performance. Starting with an overview of
the evolution of silicon process technologies, the presentation will provide
a historical context for the current state of the art. Supported by examples
from three decades of communications circuit and system design evolution,
the presentation will detail the elements required to develop SoC products
that meet the power requirements of next-generation electronics equipment.
Mehdi Hatamian (Fellow IEEE)
received a B.S. degree in Electrical Engineering from Sharif University of
Technology in Tehran, Iran in 1977, and M.S. and Ph.D. degrees in Electrical
Engineering from the University of Michigan in Ann Arbor, in 1978 and 1982
respectively. From 1978 to 1982, he worked for NASA’s Space Shuttle program,
developing hardware and software designs to support in-flight biomedical
experiments. From 1982 to 1991, he was a member of the Visual Communications
Research and the VLSI Systems Research departments of Bell Laboratories,
where he was named Distinguished Member of the Technical Staff in 1988. From
1991 to 1996, he was Vice President of Technology at Silicon Design Experts,
Inc., a company he co-founded. Since 1996, he has been with Broadcom
Corporation where he is currently the Vice President of Engineering for DSP
Microelectronics Technology. His areas of expertise are high-speed VLSI
signal processing, image processing and compression, full-custom and low
power circuit and architecture design, adaptive filtering, Gigabit Ethernet
transceiver design, high-density deep sub-micron CMOS design, high
temperature superconductors, and biomedical electronics. He has published
nearly 50 papers in his areas of expertise and holds 26 patents with several
patents pending. He is an IEEE Fellow and received his Fellow award for his
contribution to the design of high-performance digital signal processors. He
has participated in numerous national and international conferences and
other professional activities in his field as an organizer, session chair,
panelist, invited lecturer, and moderator.
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1:30 pm - 3:00 pm |
Memory
sub-system Advances and Trends
Track Chairman: Dr. Raman Menon Unnikrishnan. Dean of the College of
Engineering and Computer Science, California State University, Fullerton |
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Dr. Raman Menon Unnikrishnan. Dean
of the College of Engineering and Computer Science, California State
University, Fullerton
Track Chairman
Dr. Raman Menon Unnikrishnan
is Professor of Electrical Engineering and Dean of the College of
Engineering and Computer Science. He is active in teaching and research in
the areas of Control Systems, Power Electronics, and Signal Processing and
is an author of numerous research papers and presentations in these areas.
He has been a consultant to several industries and governmental agencies and
has been involved in technical and professional education for industries. He
is active nationally in the field of Engineering Education and Engineering
Accreditation. Prior to joining Cal State Fullerton, Dr. Unnikrishnan was on
the faculty of the Rochester Institute of Technology in Rochester, New York,
where he also served as Associate Dean for Graduate Studies and Research for
the College of Engineering from 1989 to 1991 and as the Head of the
Electrical Engineering Department from 1991 to 2001. He received his BS
degree from the University of Kerala, India, his MS from South Dakota State
University, and his Ph.D. degree from the University of Missouri, all in
electrical engineering. Dr. Unnikrishnan is a member of Eta Kappa Nu, Tau
Beta Pi, ASEE, and a Senior Member of IEEE. |
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1:30 pm - 2:00 pm
Keynote |
Dr.
Tadao Nakamura, Professor of Computer Science Tohoku University, Japan.
Laureate of IEEE Taylor L. Booth Award IEEE Fellow.
"Toward Low-Power and High-Speed Memory-Based Computing
Chips"
Low-power and high-speed computing issues are described based
on truly memory-based chips thinking of power consumption and architecture.
Tadao Nakamura received his PhD in Electronics using Computer Aided Design
in 1972 from Tohoku University. Dr. Nakamura is currently a Professor of the
Department of Computer and Mathematical Sciences at Tohoku University. He
was founding chair of the department in 1993. Prior to that he was a
Professor of the Department of Mechanical (Machine Intelligence and Systems)
Engineering at Tohoku University and a Visiting Lecturer in the Department
of Information Science at the University of Tokyo. From 1994-98 he was a
Visiting Professor of Electrical Engineering at Stanford University. His
recent research interests are in computer architecture, especially
pipelining based microarchitecture, and low power concepts in chips, in
general. He was elected in 2004 to receive the IEEE Computer Society Taylor
L. Booth Award. He has been Organizing Committee Chair of the IEEE COOL
Chips conference series fully sponsored by the IEEE Computer Society. He was
also a Program Committee member of the IEEE HOT Chips 15. Dr. Nakamura was
elected Fellow of the IEEE in 2002 for contributions to pipelined computer
architecture and computer engineering education.
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Dr.
Pierre Fazan, Founder and CTO, Innovative Silicon.
"How
to Cut Die Cost in Half"
Effectively managing die size is an important consideration
for System on Chip (SoC) designers, and the function that consumes the most
silicon is memory. The requirement for large and increasing amounts of
embedded memory has become a key factor in SoC design, and an important
consideration for designers looking to minimize their die costs. As such,
there is a large market for an ultra-dense memory technology, particularly
for designs produced at the 90 nanometer and smaller nodes. This
presentation will discuss how designers can dramatically cut their die costs
by harnessing the unique capabilities of silicon-on-insulator (SOI) devices,
which can be used to store data at double the density of embedded DRAM. The
presentation will include a discussion of the performance, energy
consumption, manufacturability, and scalability of this new technology
compared to existing embedded DRAM and SRAM. In addition, we’ll discuss the
different floating body memory architectures and describe how solutions can
be optimized for speed, power, and cost.
Dr. Pierre C. Fazan was born in Lausanne, Switzerland where he obtained his
Physics diploma and Ph.D. degrees at the Swiss Federal Institute of
Technology (EPFL) in 1984 and 1988 respectively. From 1989 to 1997 he
worked as process integration engineer then manager at Micron Technology,
Boise USA, focusing on DRAM process integration. In 1997 he was named
Professor at the Swiss Federal Institute of Technology, Lausanne, EPFL,
where he taught in the field of IC manufacturing. In 2002 he
co-founded Innovative Silicon, developing a new SOI single transistor memory
technology. This company was funded in December 2003. He acted first as CEO
and is currently CTO of Innovative Silicon. He has authored or co-authored
more than 100 papers and invented or co-invented more than 150 US patents.
Dr. Fazan has served as member in program committees of the SOI Conference,
IEDM, VLSI Tech. Symp, ISIF, ESSDERC, INFOS and ECS Conferences.
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Kyle
Kirby, Engineering Manager --The 3D Stacking Development Team, Micron
Technologies.
"Osmium
Packaging Technology"
Micron's Osmium packaging technology, which borrows its name
from one of the densest natural elements known to mankind, is poised to
drive semiconductor packaging to the wafer level. Conventional packaging
methods are reaching their technological limits, and electronics
manufacturers are still demanding smaller, denser packages, improved
performance, and lower system costs. Micron's Osmium packaging technology,
with its potential to deliver extremely high-density, small-form-factor
solutions, is the right technology at the right time. Osmium technology
combines through-wafer interconnects, a redistribution layer, and
wafer-level encapsulation—along with hundreds of supporting US patents and
process engineering breakthroughs—and effectively extends the fabrication
process to finished goods. This unique blend of leading wafer-level
packaging technologies and IP promises to change the dynamics of
semiconductor manufacturing and set a new standard for semiconductor
packaging.
Kyle Kirby graduated in 1993 from Northern California's Humboldt State
University with a Bachelor of Science in Industrial Technology. He joined
Micron in 1994 pursuing a Manufacturing Engineer career, but ended up as a
Technologist in the Research and Development department. He currently holds
20 US Patents with nearly 50 more in process at the USPTO. He has been with
the Micron Advanced Packaging R&D group since its' inception and is
currently Engineering Manager of the 3D stacking development team.
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3:00 pm - 3:15 pm
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Coffee
Break |
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3:15 pm - 5:15 pm |
Network-on-Chip (NoC) Architectures for Complex SoCs
Track Chairman: Dr. Goran
Matijasevic, Director of Research Development, The Henry Samueli School of
Engineering, University of California, Irvine
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Dr. Goran
Matijasevic, Director of Research Development, The Henry Samueli School of
Engineering, University of California, Irvine.
Track Chairman
Dr.
Goran Matijasevic is Director of Research Development at The
Henry Sameli School of Engineering at UC Irvine. In this capacity, he works
on formation of new industry-university and academic collaborations,
especially focusing on new interdisciplinary research initiatives. Prior to
this, he was the Research Coordinator of the Integrated Nanosystems Research
Facility at UC Irvine, where he worked closely with industry partners on
making them aware of available university resources. Prior to UCI, he worked
as a senior engineer at QPlus, a telecommunications start-up company. From
1994 to 2001, he was at Ormet Technologies, where as Director of Research he
was working on development of polymer and metal materials and structures for
electrical interconnect of high density circuits, new metal alloys for use
in conductive adhesives, materials for embedded passive components and heat
sensors, and high thermal efficiency electronic substrates. ¨He managed
multiple SBIR projects that led to several industry consortia projects, as
well as a license agreement with a Fortune 100 company. He has 4 U.S.
patents, 3 book chapters, and over 40 conference and journal publications
and has served on the NEMI Industry Roadmap committee. He served as
NanoWorld Conference Technical Chair, the Electronic Components and
Technology Conference (ECTC) Interconnect Chair and Emerging Technologies
Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical
Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing
Committee. He is currently on the OCTANe (Orange County Technology Action
Network) Operations Committee. Goran received his PhD from UC Irvine in
Electrical and Computer Engineering and his MBA from Pepperdine University.
He is also a member of the TriTech Advisory Board, Tech Coast Venture
Network, Life Sciences Industry Council (LINC), IEEE, and ASME.
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Marcello
Coppola, ST Microelectronics
"Exploiting
Interconnect-Centric Structural Regularity for Cost-Efficient SoC Design"
In this presentation we examine existing efforts towards
bridging the SoC design gap between electronic design automation tools and
deep submicron silicon technologies for building next generation,
heterogeneous multiprocessor SoCs. We claim that cross fertilization from
multidisciplinary domains, such as design for manufacturing, IC design flow
based on regular fabrics, system-level IP reuse, parallel and distributed
processing, computer networks, operating systems and software architectures
together with a strive for regularity may lead to innovative design
techniques that would improve productivity of complex cost-efficient SoCs.
Focusing on a modern packet-switched network-on-chip implementation, we
explore structural regularity in technological, architectural, topological,
algorithmic and application features that simplify interconnect and network
interface realization and improve system concurrency using efficient
routing, intensive communication and synchronization algorithms. By
embedding multi-dimensional regularity mechanisms within application
domain-specific design paradigms and tools we can enable full-scale
integration of complex multiprocessor SoCs with increased design complexity
and growing variability. These SoC architectures will scale at 45 nm and
below by using an interconnect-centric network-on-chip design methodology
with a regular fabric that will also help resolve manufacturing problems and
provide higher yields.
Marcello Coppola received the Laurea degree in computer science from Pisa
University, in 1992. Previously, he was with the Transputer architecture
group at the INMOS in Bristol (UK) working on the architecture of the C104
router. He is now head of the Grenoble Research Laboratory of “Advanced
System Technology”, a corporate research organization within ST
Microelectronics, and currently responsible for the STNoC project. His main
duties are budget management, coordination of several external research
groups and open communication through technical articles, ST press
announcements, etc. His research interests include design methodologies for
system-on-chip, with particular emphasis to network-on-chip, MPSoC
architecture, program modeling and system level design. His research focuses
discrete-event simulation, real-time operating systems, system-on-chip
modeling, SoC architecture and on-chip communication networks. He has
published research articles in various books and journals. He was a member
of the OSCI language working group contributing towards SystemC2.0
definition and OSCI standardization. He has been chair of many international
conferences on SoC design and has helped in organizing several others. He
has been a program committee member of DATE, FDL, CODES+ISSS and DAC and has
contributed to the MEDEA+ EDA Roadmap, as well as the SystemC
standardization.
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Jeff
Haight, Director Technical Marketing & Zainab Al-Shamma, Field Applications
Engineer. SONICS Inc.
"Abstraction Levels for SoC Memory Subsystem Design with MemMax."
The sheer complexity of present day System-on-Chips (SoCs) requires
designers to make implementation decisions at multiple abstraction levels in
order to optimize the overall architecture of the SoC. Analogous to the
multiple abstraction level of multi-core SOC interconnects and processors,
there is a need to have similar abstraction levels of the memory subsystem
for an intelligent system-level view to enable more efficient scheduling and
better Quality of Service (QoS) for the different cores. Flexibility of the
abstraction levels in a memory subsystem is key to tailoring enhanced memory
utilization for the various applications, and is essential to optimal
performance in systems with heterogeneous requirements (different speeds,
endianess, QoS, security requirements, etc.), e.g., involving bursty H.264 /
DVB video. The Sonics MemMax IP, an intelligent memory scheduler, provides
tuning capabilities that leverages the states of both the physical memory
sub-system (memory and memory controller) and the system-level processors
for optimized traffic management and efficient memory utilization. Sonics
MemMax allows the SoC integrator to easily balance the trade-offs between
area, performance, and power for overall system efficiency and robustness.
Jeff Haight: Jeff is currently the Director of Technical
Marketing for Sonics, Inc., the leader in IP generation for high performance
SoC interconnects. He has been in the electronics industry for over 3o
years, having participated in communications and RADAR signal processing
system design and design management, and various technical marketing,
business development, and engineering management roles in semiconductors,
CAD development, and IP marketing at LinkaBit, TSC, TRW, Zoran, VLSI,
Compass Design Automation, and Toshiba. He has published over 25 articles
and conference papers. Jeff enjoys reading, tennis, skiing, and music in his
not-so-copious free time and when not chauffeuring his two teenagers to or
from some destination.
Zainab Al-Shamma: Zainab is currently a field applications
engineer at Sonics, Inc.; responsible for creating evaluation demos and
training materials to help customers use Sonics products most effectively.
She also worked as a design services engineer for the company, helping to
design a customized crossbar and helping to integrate and optimize the
SonicsMX® interconnect into customer’s complex SoC designs. Previously,
Zainab was a member of the technical staff in ASIC development at Luminous
Networks and at Silicon Graphics, and she served as an intern at
IBM/Somerset Design Center and STAR Laboratories at Stanford University. She
is proficient in a number of industry software tools including Verilog,
Synopsys, Verisity and Magma. Zainab holds a B.S. degree in Electrical
Engineering from Stanford University.
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Dr.
Nader Bagherzadeh,
University of
California, Irvine
"Design
and Analysis of A Network-on-Chip (NoC) Processor Architecture"
In this talk I will present our work on the design and modeling of a NoC
based architecture called MaRS. The work covers system level modeling and
performance evaluation of the proposed architecture for high performance and
low power applications in communication and multimedia processing.
Dr. Nader
Bagherzadeh has been involved in research and development in the areas of
computer architecture, reconfigurable computing, VLSI chip design, and
computer graphics. For almost ten years ago, he was the first researcher
working on the VLSI design of a Very Long Instruction Word (VLIW) processor.
Since then, he has been working on multithreaded superscalars and their
application to signal processing and general purpose computing. His
current project at UC, Irvine is concerned with the design of coarse grain
reconfigurable pixel processors for video applications. The proposed
architecture, called MorphoSys, is versatile enough to be used for digital
signal processing tasks such as the ones encountered in wireless
communications and sonar processing. DARPA and NSF fund the MorphoSys
project (total support $1.5 million). Dr. Bagherzadeh was the Chair of
Department of Electrical and Computer Engineering in the Henry Samueli
School of Engineering at University of California, Irvine. Before
joining UC, Irvine, from 1979 to 1984, he was a member of the technical
staff (MTS) at AT&T Bell Laboratories, developing the hardware and software
components of the next-generation digital switching systems (#5 ESS).
Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of
Texas at Austin. As a Professor, he has published more than a hundred
articles in peer-reviewed journals and conference papers in areas such as
advanced computer architecture, system software techniques, and high
performance algorithms. He has trained hundreds of students who have
assumed key positions in software and computer systems design companies in
the past twelve years. He has been a Principal Investigator (PI) or
Co-PI on more than $2.5 million worth of research grants for developing
next-generation computer systems for solving computationally intensive
applications related to signal and image processing.
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Dr.
Fabrizio Petrini,
Pacific Northwest National Laboratory.
"Communication
Analysis of the Cell Broadband Engine Processor"
The
existence of major obstacles to the traditional path to processor
performance improvement has led chip manufacturers to consider multi-core
designs. These architectural solutions promise a variety of
power/performance and area/performance benefits. But additional care must be
taken to ensure that these benefits are not lost due to inadequate design of
the on-chip communication network. This paper presents the
design challenges of the on-chip network of the Cell Broadband Engine (Cell
BE) processor, and describes in detail its architectural design and the
network, communication and synchronization protocols. In the experimental
evaluation, performed on an early prototype, we analyze the communication
characteristics of the Cell BE processor, using a series of microbenchmarks
involving various DMA traffic patterns and synchronization protocols. We
find that the on-chip communication subsystem is well matched to the to
computational capacity of the processor. A Synergistic Processing Element (SPE)
can issue an internal direct memory access (DMA) operation in less than 4
nanoseconds, and a DMA of a single cache line can be executed in less the
than 100 nanoseconds. SPEs can achieve the optimal bandwidth of 25.6
GB/second in point to point communication with surprisingly small messages
-only a few KB, using batches of non-blocking DMAs. The aggregate network
behavior under heavy load is also remarkably efficient, reaching almost 200
GB/second with collective patterns and optimal contention resolution under
hot-spot traffic.
Fabrizio Petrini is a laboratory fellow in the Applied Computer Science
Group in the Computational Sciences and Mathematics Division at Pacific
Northwest National Laboratory (PNL). Before his appointment at PNL, he was a
member of the technical staff of the CCS3 group of the Los Alamos National
Laboratory (LANL), a research fellow of the Computing Laboratory of the
Oxford University (UK), a postdoctoral researcher of the University of
California at Berkeley, and a member of the technical staff of the Hewlett
Packard Laboratories. His research interests include various aspects of
supercomputers, including high-performance interconnection networks and
network interfaces, fault-tolerance, job scheduling algorithms, parallel
architectures, operating systems and parallel programming languages. He
received numerous awards from the Derpartment of Energy (DOE) for
contributions to supercomputing projects, and from other organizations for
scientific publications.
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5:15 pm - 6:15 pm |
Panel: Architectural and Performance-Related Challenges for Complex
SoCs
Moderator: Ron Wilson,
Executive Editor, EDN Worldwide.
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Ron Wilson, Executive Editor, EDN
Worldwide.
Moderator
Ron Wilson, EDN's executive
editor, boasts a checkered career reaching back to the dawn of medium-scale
integration, whatever that was. As a design engineer for Tektronix, Inc. he
developed bus interfaces and participated in processor- and graphics-engine
architecture and design, as well as evaluation engineering and
software-driver development. The most tangible project in which he
participated led to—arguably—the first engineering workstation, unknown
today except for its minor supporting role in the original Battlestar
Galactica television series.
Later an exile from engineering, Ron wandered through the realms of training
and marketing before landing happily in the editorial world, first with
Computer Design Magazine in the mid-1980s. From there he moved to CMP Media,
where he wrote for EE Times and was briefly involved with ISD Magazine. His
primary interests are system design based on highly-integrated ICs, the
interaction of chip and software engineering and the future of design
practice in the increasingly global electronics community.
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Dr. Marco Racanelli, Vice
President of Technology and Engineering, Jazz Semiconductor.
Panelist
Dr. Marco Racanelli is the
Vice President of Technology and Engineering at Jazz Semiconductor, an
independent pure-play wafer foundry focused primarily on specialty CMOS
process technologies optimized for the manufacture of highly integrated
analog and mixed-signal semiconductor devices. His responsibilities include
leading technology development, modeling, design automation and design
service teams. Before joining Jazz in 2002, Dr. Racanelli held
technology and engineering positions at Conexant Systems. He also held
management positions with Rockwell Semiconductor Systems prior to the
Conexant spin-off in January 1999. He joined Rockwell in 1996 and has since
held several posts of increasing responsibility in the area of technology
development. In these positions, Dr. Racanelli helped establish
industry leadership in SiGe and BiCMOS technology, and was instrumental in
building a strong design support organization for Jazz Semiconductor. Prior
to joining Rockwell, Dr. Racanelli worked at Motorola, Inc., where he
contributed to bipolar, SiGe and SOI development for Motorola’s
Semiconductor Products Sector. He has authored or co-authored more than 50
technical publications and holds 30 U.S. patents. Dr. Racanelli
received his Ph.D. and M.S. degrees in Electrical and Computer Engineering
from Carnegie Mellon University, and his B.S. degree in Electrical
Engineering from Lehigh University.
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David Fritz, Chief Executive Officer,
Silistix, INC.
Panelist
David Fritz is Chief Executive
Officer of Silistix, the worlds first clock-less on-chip interconnect
company. Prior to joining Silistix, Fritz was vice president of marketing
and business development for ARC International. He was the founder and
president of Production Languages Corporation, a pioneer in configurable
processor technology, where he was awarded a U.S. patent covering
fundamental processes related to configurable processors. In 1999, ZILOG
acquired Production Languages, naming Fritz the vice president of ZiLOG’s
Advanced Cores R & D as well as vice president of ZiLOG’s Development
Systems Group. Fritz holds degrees in Mathematics and Computer Science from
Manchester College.
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Larry Morrell, Vice President of IP Products,
Impinj Inc.
Panelist
Larry Morrell has over 20
years of semiconductor-industry experience in engineering, management, and
marketing roles. He directed marketing at Cypress for their programmable
clocks division and market-leading USB chips. Prior to that he was the Vice
President of Marketing and Business Development for Data I/O where he helped
popularize FPGAs and co-founded an industry trade show. Earlier in his
career he established a European sales and marketing operation in Paris for
an IC startup called Seattle Silicon and worked in engineering and
management at Boeing. Mr. Morrell earned a B.S. in Computer and Electrical
Engineering and a B.A. in Russian Languages from New Mexico State
University.
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Bill Chown, Director of Engineering, Mentor
Graphics. Representing SPIRIT Consortium.
Panelist
Bill Chown, currently a
product group director for the system-level engineering division at Mentor
Graphics, moved to the semiconductor industry with Intersil Semiconductors,
where he went from designing mixed signal and DSP systems, at chip and board
level in the UK, to managing projects through to layout and production test.
He subsequently worked in EDA and test software development in Europe and
the US with Mentor Graphics, Summit Design/TSSI, Integrated Measurement
Systems and Credence. A twenty-five year veteran, Bill currently specializes
in TLM and RTL platform-based design and verification. He has been involved
with standards activities for several years, serving in the CFI, ECSI, and
STIL initiatives, is past chair of the TTTC TAC on Virtual Test, is
currently a member of the STIL working group, and is a board member for The
SPIRIT Consortium and for OMG. Bill earned an Electronic Engineering degree
from the University of Wales and an MBA from the University of Oregon.
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Paolo Cocchiglia, Vice President, ADS
(ASIC Design and Security)
Infineon Technologies North America Corp.
Panelist
Paolo Cocchiglia is currently
Vice President of the ADS (ASIC Design and Security) business group at
Infineon Technologies North America Corp. Prior to joining Infineon, from
1993 till 2003, Cocchiglia held various managerial positions at ST
Microelectronics, both in Italy as well as in San Jose, Calif. He was
program manager at ST Microelectronics in Italy, then assumed Business
Development Engineering, Product Marketing and Strategic Marketing Director
positions in the San Jose office. Cocchiglia’s other professional experience
consists of positions at Seleco and Fontilevissima, where he held consultant
positions, and Venture, where he was Design Engineer. He holds an MBA from
Profingest Management School in Bologna, Italy, and an Electronic
Engineering degree from Padua University, Italy.
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Panelist Names |
Panel: Architectural and Performance-Related Challenges for Complex SoCs
Moderator:
Ron
Wilson, Executive Editor, EDN Worldwide.
Panelists:
1.
Mohy
Abdelgany, President and Chief Executive Officer, Newport Media , Inc.
2.
David Fritz, Chief Executive
Officer, Silistix, Inc.
3. Larry Morrell, Vice
President of IP Products, Impinj Inc.
4. Bill Chown, Director of
Engineering, Mentor Graphics. Representing
SPIRIT Consortium.
5. Paolo Cocchiglia, Vice
President, ADS (ASIC Design and Security) Infineon Technologies North
America Corp.
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4:30 pm - 8:30 pm |
Conference Exhibit & Reception Open
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4th
International System-on-Chip
(SoC) Conference & exhibit
Detailed Program Information (abstracts & bios) for Thursday, November 2, 2006* |
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8:00 am - 8:15 am |
Farhad
Mafie, President and CEO of Savant Company Inc.
"Welcome and Opening Remarks and Conference updates"
Farhad
has over 20
years of experience in semiconductor and computer businesses and more than 10
years of university-level teaching experience. Farhad is the former
Vice President of Marketing/Business Development and Technical Sales Engineering at
Toshiba America Electronic Components, Inc. He was responsible for marketing
the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth,
Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).
He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer
products & solutions based on ASSP and SoC Models.
Farhad established Toshiba's on-line
Tech-Support System as well as Toshiba's on-line System Solution Selling
methodologies for all Toshiba's products in the North American markets.
These on-line systems were adopted by Toshiba on a worldwide basis. He
also developed Toshiba's ASSP Business Unit and Technical Sales Engineering
Team as two brand new organizations for the company.
Farhad has also worked at Lucent Technologies
on marketing communications ICs,
Toshiba Information Systems on product definition for Toshiba's notebooks
and handheld products, Unisys on designing new processors and computer
systems, and MSI Data on
designing data collection products. He has a Master of Science and a
Bachelor of Science degree in Electronic Engineering from California State
University, Fullerton.
His combined business and academic experience has
given Farhad a unique ability to effectively communicate complex new
technologies to business professionals at all levels, as well as the ability to
foresee emerging leading-edge technologies.
Farhad is an author and a
translator, and he writes articles for a variety of journals and Web-based
magazines on technology and political affairs.
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8:15 am - 12:00 pm |
Semiconductor Trends
and New Design Approaches for Complex SoCs
Track Chairman: Farhad Mafie,
Savant Company Inc.
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Francis
Chow, Business Development Manager, Altera.
"HardCopy Structured ASICs A Superior Design Flow."
A Superior Design Flow Many designers face a dilemma at the
beginning of a project. They can either create innovative products fast
using expensive FPGAs, or use a long, effort-intensive standard cell ASIC
design flow to target the lowest possible cost.
Some companies try to do both by designing twice – once for an FPGA
prototype and another for the low cost ASIC. The result can be a very
expensive process with little chance of reducing the development risk.
The best of all worlds is a design environment that supports FPGA
development and seamless migration to a low cost ASIC solution. The
combination allows companies to generate breakthrough designs, test them in
the market, add features and functions in real time to respond to industry
demands, then produce a single product that supports a wide range of market
segments. Alternatively, they can generate several variations each of which
support a single market or application. If designs prove popular, companies
can migrate them easily to a high-volume, low-cost structured ASIC with no
disruption of deliveries. Now companies can get the performance they need
for today’s designs and get them to market in a low risk, cost effective
process. Companies can take advantage of Altera’s HardCopy II structured
ASIC family that supports about 3.6M ASIC gates and 8.8M RAM bits, running
over 350 MHz performance. Once the design is fully verified in the FPGA, the
designer can submit it to Altera’s HardCopy Design Center, and receive
HardCopy II prototype devices within 10 weeks. HardCopy II devices require
50-70% lower power than an FPGA, which also means lower cost for such items
as cooling fans and heat sinks. Altera provides that best-of-all-worlds
solution and companies are employing the new alternatives it offers for both
OEM systems and for ASSP development.
Francis Chow is a business
development manager at Altera and has extensive experience in the
semiconductor and electronic design automation (EDA) tools industries. At
work, he is responsible for identifying and evaluating semiconductor and EDA
startups for M&A, equity investment and partnership opportunities. Before
Altera, Francis led a design team at Texas Instruments’ Broadband
Communications Group on DSL and VoP chipsets. During his tenure, TI achieved
#1 market share position in both DSL and VoP markets. Francis received his
BSEE from Rensselaer Polytechnic Institute and his MSEE from University of
California at Berkeley. He is currently pursuing his MBA at Haas School of
Business, University of California at Berkeley, on a part-time basis.
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Rick
Mosher, IP Product Manager, Structured Digital Products. AMI Semiconductor
"Pre-Mature Claims to Structured ASIC Demise"
The death of the structured ASIC has been greatly over
exaggerated and is not imminent. In fact structured ASIC technology is
evolving into a semiconductor product that fits, exceedingly well, into
specific market niches. With all of the negative press surrounding
structured ASICs, recently, it is easy to understand how people can come to
the conclusion that structured ASIC technology is dying. However, this paper
will explore the problems seen so far with structured ASIC products; compare
and contrast structured ASICs with their semiconductor counterparts; and
finally explain why structured ASICs are here to stay and where they fit
within the current market space. Outline:
I. Introduction, II. Exploring the Issues Surrounding Structured ASIC
Products, III. Comparing Different Technologies (SA vs. SC vs. ASSP),
IV. Examining the Structured ASIC Market (A. Mid-range ASIC market, B. FPGA
conversion market), V. Conclusion.
Rick Mosher has more than ten years of engineering experience managing the
design, verification and integration of complex digital logic blocks used to
facilitate and enable multi-million dollar digital products. With a
focus on FPGA, ASIC and PCB design coupled with product management and
strategic marketing, Mosher possesses the skills necessary to aid AMI
Semiconductor in developing digital IP roadmaps, analyzing market data and
providing customer support for the Structured Digital Product business unit.
Prior to his role as product manager at AMI Semiconductor, Mosher was a
senior member of the design team responsible for the development of digital
hardware used to enable TDMA and CDMA wireless systems for Nortel Networks.
During his tenure at Nortel, Mosher was responsible for FPGA, ASIC and PCB
design. Additionally, Mosher was the verification prime on the team,
responsible for the system level verification of multi-million gate ASIC
designs. A published writer and expert speaker, Mosher’s education has
been focused on telecom and computer engineering.
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Gordon
Mortensen, Engineering Director - Advanced Power, National Semiconductor
"Low Power SoC Design Using Multiple Voltage Islands and
Adaptive Voltage Scaling"
SoC architectures with multiple voltage islands and the
application of Adaptive Voltage Scaling (AVS) can greatly reduce power
consumption and improve energy efficiency in SoC designs. This
discussion/paper will present simulated and measured power savings with AVS
and investigate voltage island partitioning options for low power SoC
design.
Gordon Mortensen is an Engineering Director in the Advanced Power Group at
National Semiconductor. He has 23 years of experience in the semiconductor
industry in engineering management, as a design engineer, and as a product
engineer. Gordon's embedded systems experience includes 4 bit, 8 bit and 16
bit micro-controller products, x86 platform chipsets and PowerWise(R)
Portable Power Management products.
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9:45 am - 10:00 am |
Coffee
Break |
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10:00 am - 10:30 am
Keynote |
Ana
Molnar Hunter, Vice President of Technology, Samsung Semiconductor,
Inc.
"Lessons learned at 65nm that will be applied to 45nm"
TAs 65-nanometer process technology pushes the
power/performance curve, the economics of volume production come into play
as critical element in semiconductor chip design and manufacturing. The
upfront costs to begin the design cycle have skyrocketed such that customers
must be able to see their product into high volume production quickly. To
allow customers to amortize those initial costs and see a sizable return on
their investment, the whole semiconductor foundry ecosystem – from DFM
design firms to the manufacturing companies – needs to remain on the same
roadmap. Semiconductor foundry companies can’t operate in a vacuum. At
advanced technology nodes such as 65nm and sub-65nm, the design complexity
demands that the foundry have the design and manufacturing expertise of an
IDM mixed with the services of a pure-play. With 65nm becoming more
mainstream, the industry will take the lessons learned and apply those 45nm.
Consumer electronics and high-speed computing/networking will be the
beneficiaries of the advanced process technology work being done now. This
keynote address will focus on the following:
1-Business/economic trends for those customers looking to engage in a 65nm
chip design;
2-The need for the foundry ecosystem to stay on the same roadmap and provide
an open platform for customers; and,
3-Lessons learned at 65nm that will be applied to 45nm.
Ana Molnar Hunter is vice president of Technology for Samsung Semiconductor,
Inc.’s System LSI foundry business. Leading the US business development
team, Hunter is responsible for Samsung’s foundry customer activities in
North America. She is also responsible for setting the strategic development
direction of the North America foundry business. Prior to joining Samsung,
Ms. Hunter spent the last 15 years working in the semiconductor foundry
industry in various positions as a consultant, vice president of U.S.
operations for Communicant Semiconductor Technologies AG, Germany, and vice
president of EDA and customer services for Chartered Semiconductor, Inc. She
holds a B.S. in chemistry from Duke University.
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Ray
Abrishami, Senior Director of Wireless Business Group, Fujitsu
Microelectronics America, Inc.
"CMOS, Scaling, and the Future CMOS Scaling. Has it bottomed
out?"
Scaling, one of the most pivotal transformations in the
silicon technology occurred in such an unglamorous, subtle, persistent and
gradual manner, that the technology genius behind it never received the
accolades it so richly deserves. For some decades now, we have relegated the
silicon scaling to somewhat routine factory automation and manufacturing
evolution, taking it for granted, and thinking of it as an endless path for
further leveraging the silicon technology. Scaling concept was a result of a
quest for cost and performance optimization. This marvel of a technological
endeavor has been singularly responsible for providing affordable portable
electronic equipment to the consumers, delivering such astonishing level of
functional complexity and performance that was unimaginable a relatively
short time ago. The key questions before us now are: has the technology
scaling bottomed out? And how much longer can we continue on the scaling
path? These are intriguing questions that are worth exploring as we embark
on introducing the 65 nm technology node and beyond. At its inception, it
was clear that CMOS would be an ideal technology for scaling. Providing a
relatively simple basic switch structure initially facilitated an ad-hoc
selective two dimensional scaling, soon to be followed by three dimensional
scaling of geometries and design rules. Earlier predictions warned about
runaway power dissipation as functional density and frequency of operation
increased. As time has shown, we were able to achieve close to full scaling
of the technology which included scaling down the power supply (vdd). In
addition, deployment of new design methodologies for power and clock
distribution/ management coupled with proper use of asynchronous design
techniques and availability of innovative packaging technologies have
allowed us to pack tens of millions of devices on a single piece of silicon
for operation at gigahertz (and higher) clock rates. While we
recognize that there are theoretical as well as practical limits to scaling,
at the same time such challenges present new opportunities which would
enable us to achieve the levels of integration up to billion devices (gigascale)
or even to contemplate designing and building chips with trillion devices (terascale).
Contemplating such possibilities would make CMOS scaling seem endless.
However, the notion of scaling as we know it today will change to a higher
plateau of sophistication and complexity even before we reach the
fundamental physical limits. A few examples follow:
The future CMOS scaling must overcome many challenges. As dimensions get
smaller and smaller, we must find ways to reliably transfer component images
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