Agenda

Abstracts & Bios

Registration

Information

List of Table-Top Exhibit

Rent An Exhibit Table

Register for Free Exhibit Pass

Sponsors & Presenting Companies

Detailed Program Information (Abstracts & Bios) for wednesday, November 1, 2006*

8:00 am - 8:15 am

Farhad Mafie, President and CEO of Savant Company Inc.

"Welcome and Opening Remarks, Technology/Market Trends."

Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models.

Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis.  He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company.  

Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.

His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies.  

Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

  8:15 am - 12:00 am

New CPU and DSP Cores for Complex SoC Applications

Track Chairman: Shay Gal-On, EEMBC Director of Software Engineering & Leader of EEMBC Technology Center

Shay Gal-On, EEMBC Director of Software Engineering & Leader of EEMBC Technology Center.

"Track Chairman"

Shay Gal-On is EEMBC’s Director of Software Engineering and leader of the EEMBC Technology Center. Previous to joining EEMBC, he was Principal Performance Analyst in the Microprocessor Products Group at PMC Sierra, and his career has also included roles as a software engineer for Improv Systems and Intel.. A compiler/tools expert, he has devoted considerable effort to analyzing the effects of various compilers on benchmark performance and has ported the EEMBC benchmarks using Wind River Diab, Green Hills MULTI, ARM.RVDS, Improv Jazz tools, the Stretch/Tensilica development environment, and many versions of gcc. He has also served as a member representative on the EEMBC Board of Directors and thus is well acquainted with EEMBC processes, having ported and optimized the benchmarks for a wide variety of architectures. 

Dr. Gheorghe Stefan, Chief Scientist & Co-Founder, Connex Technology, Inc.

"The CA1024 :SoC with Integral Parallel Architecture for HDTV Processing"

The CA1024 SoC is the commercial implementation of an Integral Parallel Architecture, centered on ConnexArrayTM (a massively data-parallel processor), a time-parallel speculative array, and a Multi-Threaded host engine (MTH), providing the programmable media processor architecture developed by Connex Technology, Inc. The chip is described and its performances in the video decoding domain are presented.  Why an Integral Parallel Architecture?  Because digital video work loads (as almost any complex real application) exhibit significant data parallel block-transform-based computation in combination with inherently serial recursive entropy coding/decoding workloads. Accordingly, the system must be optimized for vector processing and stream processing, as fully programmable resources for data parallel and speculative time parallel computing, respectively. More, the real time application in HDTV consists in few distinct functional threads such as stream demultiplexing, audio and video.  Data Parallel Resources:  ConnexArray™ (CA) is a linear array processor comprised of 1024 simple and small processing elements (PEs). Two stack processors control the CA: Instruction Sequencer (IS) and Input/Output Controller (IOC). The IS issues one instruction for all PEs in each cycle. The instruction is executed by each PE according to its internal state. In parallel, the IOC controls the transfer of vectors between CA and the external memory. At 200 MHz, CA provides 200 GOPS (>40 GOP/Watt), 400 GB/sec internal bandwidth, and 3.2 GB/sec external bandwidth. Time Parallel Resources:  Speculative Accelerator is an optimized engine for the intrinsically serial entropy coding or decoding algorithms associated with advanced video compression & decompression. It is a MIMD array of eight elements capable of processing in real time two H264 HD video streams.  How CA1024 is Programmed:  The Connex Programming Language (CPL) is based on the familiar C/C++ syntax. It hides the complexities of the parallel execution hardware. The first version of CPL addresses the needs of video applications by providing support for operations on vectors made up of 16-bit components (integer and fixed-point). An I/O library provides a number of functions that are optimized for video applications. All calls are non-blocking (i.e. asynchronous), because they are run on IOC strictly in parallel with CA/IS code. :  CA1024 performance for video-centric algorithms.  Our performance analysis predict that with the dual HDTV codec H.264 or VC1 advance video decode, the CA1024 has ample headroom to inject error resiliency, color management, scaling and de-interlace processing. For some basic functions involved in HDTV processing we have:  Pixel-based motion detection: 0.04 clock cycles / pixel or 2400 FPS. 8x8 IDCT: 5 clock cycles / block.  SAD: 1.25 clock cycles / block 16x16


Gheorghe Stefan, PhD, Chief Scientist & co-Founder,  Gheorghe Stefan has over 30 years of experience in teaching, research and industry roles including digital design and computer architecture. He has developed the architectural and structural design and basic algorithms of the ConnexArrayTM architecture. Prior to found Connex Technology, he designed and implemented a version of the Lisp Machine, initiated the design of ConnexArrayTM, and authored more than 15 books and 100 articles on digital design & computer architecture. He is also teaching at the Politehnica University of Bucharest, Romania where he serves as a tenured professor in electronics and computer engineering and received his PhD in electronics.

Mike Butts, Architect, Ambric, Inc.

"Implementing A New, Massively-Parallel, MIMD Computing Fabric SoC "

Ambric has developed the first globally-asynchronous, scalable, software-programmable teraOPS IC platform. Ambric has also solved the programming challenge of developing and testing general-purpose massively-parallel, MIMD applications. Ambric’s architecture offers a significant price-performance advantage over high-end DSPs and FPGAs, and can keep pace with the exponential growth of Moore’s law.

Mike Butts: Butts came to Ambric from another programmable IC platform company that he co-founded. He has a rich background in architecting large-scale reconfigurable hardware. In the 1980s, he co-invented hardware logic emulation using reconfigurable hardware -- technology that has developed into a $100 million per year market. Butts developed a number of reconfigurable chips and system products in his twenty-year career in the electronic design automation industry, including stints at Mentor Graphics Corporation, Quickturn Design Systems, Synopsys, Inc., and Cadence Design Systems, where he was a Cadence Fellow. Butts' roots are in advanced computer architecture, which he further developed while at Floating Point Systems, Beaverton, Ore. He holds a B.S. and an M.S. in Electrical Engineering and Computer Science from M.I.T.

Steve Steele, Director of Business Development, Data Engines, ARM Ltd

"Delivering Data Engine Benefits in the System Context."

Over recent years, there has been a steady progression towards design platforms that enable high-performance, feature-rich products to be introduced to the market in rapid succession. As companies seek to further differentiate their products, they require higher levels of audio, image and video quality to be incorporated within the latest designs and are turning to specialized DSP solutions to fulfill their needs.

ARM Data Engines are increasingly being integrated into SoCs to provide the necessary specialised data processing that delivers an optimal balance of high performance, low power consumption and less area (better PPA). Data Engine designs, based on ARM's proprietary OptimoDE technology, are available across a wide range of applications.

Because system integration occurs towards the end of the design process, it is most important that process runs smoothly; the cost of schedule delays can be immense. ARM seeks to provide technologies that provide a comprehensive solution for integrating its data engines in a systematic and system-programmable way into the SoC. It is essential that the compelling PPA benefits of data engine technology are preserved when integrated within the SoC and when programmed at the system-level.

An example of ARM's data engine technology is AudioDE(tm), an application class-specific data engine that is tailored for embedded Digital Signal Processing (DSP) in portable audio applications. The combination of architectural properties and the highly parallelizing compiler yield a solution that results in minimal power and area requirements for audio applications. The AudioDE product connects into ARM's broad ecosystem of simulation, modeling, debugging, software and hardware to provide for efficient, seamless integration.

ARM will discuss the company's approach to implementing such domain-specific applications into today's consumer devices and how the company is delivering optimized performance levels of dedicated logic with re-programmability of general purpose DSP solutions.

Steve Steele joined ARM in 2001, initially working as a program manager for Java. Steve then moved on to managed a team looking after ARM's software business that included Java, power management and security products. More recently, Steve moved over to ARM's Data Engines Division to drive business development.  Before joining ARM, Steve worked at Thales Optronics where he managed the design and build of a new EO reconnaissance system for the Royal Air Force. Prior to that, Steve worked at Vinten where he worked on embedded hardware and software design, system design and product marketing in the broadcast television industry.  Steve holds a BSc (Hons) in Physics with Physical Electronics from the University of Bath, and an MBA from Nottingham Business School.
 

Keynote

Arup Gupta, Director, Wireless Platform Technology at Mobility Group, Intel

"Advances in packaging, CMOS design and flexible architectures for new ultra-mobile PC (UMPC)"
 

Dr. Dominik Schmidt, Intel

Wireless technology has been evolving across various vectors from cellular networks to wireless short range personal area networks to wireless broadband networks. As we move to the third decade of commercial wireless technology deployment, there is a growing trend for a multitude of these technologies emerging on individual client platforms. Network providers are looking for the best possible connection with lowest cost per bit of data services; consumers are looking for client platforms that work together to bring unique services not possible with single networks at an affordable price. This talk will focus on new technologies for multi mode client devices, and how these technologies can extend the service providers revenue model. The goal is keeping cost of delivery of services low while providing new applications for the emerging class of client platforms.

Wireless technology is becoming pervasive, with several new standards being added to the mobile device paradigm. While single-protocol solutions still dominate, portable, multi-mode wireless is already here. For example, Intel has introduced a new ultra-mobile PC (UMPC) for Windows with up to five simultaneous wireless standards. The success of these solutions will be dictated by their low cost, small size and minimal power consumption. This talk will focus on the technology advances in packaging, CMOS design and flexible architectures necessary to achieve these difficult targets.

Arup Gupta is the Director of the Wireless Platform Technology group at Intel. Arup joined Intel in late 2002 as the CTO of the newly formed Consumer Electronics group. Prior to that he was the VP of Engineering at two startups Morphics Technology and Televersal Systems. Arup was the Engineering Director at Lucent Technologies leading Silicon and systems teams for complete reference design platforms in Consumer Wireless and Bluetooth till 2000. Arup spent over 14 years at AT&T/Lucent Bell Labs in various design and management positions. During his career he and his team have produced over 20 commercially successful DSPs, mixed signal and RF ICs. Arup's interest lies in Architecture for high performance signal processing and Reconfigurable computing. Arup has a MSEE from Washington State University and a BTech (Hons) from IIT Kharagpur, India in addition to several Executive management courses from Harvard University and Wharton School of Business. He has 3 patents awarded on DSP architectures and several patents pending. Arup is a Senior member of IEEE and a member of Sigma Xi.

Dominik Schmidt, M.S.M., Ph.D., PE, has been working in the semiconductor industry for 17 years. He was at Altera working on reconfigurable logic and has worked with Sharp, TI, Cypress, and TSMC. He cofounded Pixel Devices International (PDI) in 1997, one of the first companies to offer CMOS imaging chips. After PDI was acquired by Agilent, he founded Airify Communications, specializing in multi-protocol wireless chip design. After the acquisition of Airify, Schmidt is now at Intel Corporation leading efforts to design the next generation of advanced wireless products. He has also worked for the Stanford Linear Accelerator and Lawrence Berkeley National Laboratory on several advanced projects, and has consulted for several large companies and startups in the mixed-signal and RF design areas. He has taught at UC Extension since 2000 and also teaches at Tsinghua University in Beijing. He is writing a graduate textbook on RF Design for Elsevier Press.

Steve Leibson, Technology Evangelist, Tensilica, Inc.

"Nanometer MPSOC Design Using Configured Cores"

This presentation emphasizes a processor-centric MPSOC (multiple-processor SOC) design style consistent with the realities of 21st-century, nanometer silicon. Assignment of on-chip tasks to firmware-controlled processor cores whenever possible maximizes SOC flexibility, cuts power dissipation, reduces the size and number of hand-built logic blocks, shrinks the associated verification effort, and thus minimizes overall design risk.  Microprocessor cores vary widely in their attributes as do packaged microprocessor ICs for board-level designs and SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. This selection method assumes that the laws of the microprocessor universe have remained unchanged since Intel introduced the 4004 processor in 1971, but this assumption is no longer valid.  Existing SOC design methods attempt to match on-chip tasks to a few dissimilar, fixed-ISA processor types (general-purpose processors and DSPs), which greatly complicates software development. A family of software-compatible, configurable and configured microprocessor cores can efficiently implement a wide range of simple control, conventional DSP, and media-processing tasks while employing a consistent set of software-development tools so that programmers familiar with one processor in the family can easily switch to another.  This presentation is based on a new book, “Designing SOCs with Configured Cores,” which will be published in July, 2006 by Elsevier under its Morgan Kaufmann imprint.

Steve Leibson is the Technology Evangelist for Tensilica, Inc. He formerly served as the Vice President of Content and Editor in Chief of the Microprocessor Report, Editor in Chief of EDN Magazine, and Founding Editor in Chief of Embedded Developers Journal magazine. He has written hundreds of articles that have appeared in electronics industry trade magazines worldwide and he has won many industry awards for his writing.  While at the Microprocessor Report, Leibson developed and presented many microprocessor seminars and he organized and served as MC for the Microprocessor and Embedded Processor Forums. He holds a BSEE Cum Laude from Case Western Reserve University and worked as a design engineer and engineering manager for leading-edge system-design companies including Hewlett-Packard and Cadnetix before becoming a journalist. Leibson is an IEEE Senior Member.

Dr. Thanh Tran, Embedded Hardware Systems Manager,  Texas Instruments, Inc.

George Szanto, Vice President of Marketing, Silicon Hive

"Hitting the Sweet Spot Between Hard Wired Logic and Programmable DSPs With HiveFlex Processors"

SoC platform owners face ever decreasing time to market and time in market challenges. One solution to this dilemma is the use of application specific programmable DSPs which replace traditional hardwired logic. HiveFlex processors, delivered as soft IP, for mobile and fixed terminals reduce design cycles by up to a factor of 3 while maintaining performance, power dissipation, and area constraints found in typical high volume consumer ICs. Specific applications in communications (DTV, TvonMobile, WiMax/Wibro) and image signal processing (ISP, CMOS sensors) will be presented along with design data highlighting how such IP hits the sweet spot of current SoC platform owner’s needs.

As Vice President of Marketing For Silicon Hive George is responsible for all marketing and partnership activities worldwide. He has over 15 years of high tech marketing experience in a variety of industries spanning IP sales, security IC’s and imaging systems. Recently he held senior management positions with SafeNet and SRC Vision focusing on product management, business development and product marketing. Prior to that he owned and operated his own international technology consulting company. George holds a BA degree in applied physics from University of California San Diego augmented by business education from University of California Berkeley and Syracuse University.
 

Keynote

Dr. Mehdi Hatamian, Vice President of Engineering, DSP Microelectronics, Broadcom

"From 5000nm to 45nm: A 30 Year Journey in Chip Design
Low Power Challenges in System-on-a-Chip Design"

Increasingly complex system-on-a-chip (SoC) designs have been one of the driving forces behind the massive adoption of broadband connectivity and, by extension, Internet technologies. The ability to integrate massive mixed-signal circuits capable of higher performance and increasing functionality onto smaller and smaller pieces of silicon has enabled the proliferation of wired and wireless communications on a widespread scale. Today’s portable devices are converging into complete single-chip SoCs, adding both complexity and power challenges for the most talented chip designers. Consequently, the increasing presence of single-chip components increases the need for greater power efficiency in subsequent generations of these converging products. Although advances in silicon process geometries provide some performance improvements, they also introduce new complications that can impact the success of an SoC product.

This presentation will examine the challenges and necessities of optimizing SoC designs for improved low-power performance. Starting with an overview of the evolution of silicon process technologies, the presentation will provide a historical context for the current state of the art. Supported by examples from three decades of communications circuit and system design evolution, the presentation will detail the elements required to develop SoC products that meet the power requirements of next-generation electronics equipment.
 

Mehdi Hatamian (Fellow IEEE) received a B.S. degree in Electrical Engineering from Sharif University of Technology in Tehran, Iran in 1977, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan in Ann Arbor, in 1978 and 1982 respectively. From 1978 to 1982, he worked for NASA’s Space Shuttle program, developing hardware and software designs to support in-flight biomedical experiments. From 1982 to 1991, he was a member of the Visual Communications Research and the VLSI Systems Research departments of Bell Laboratories, where he was named Distinguished Member of the Technical Staff in 1988. From 1991 to 1996, he was Vice President of Technology at Silicon Design Experts, Inc., a company he co-founded. Since 1996, he has been with Broadcom Corporation where he is currently the Vice President of Engineering for DSP Microelectronics Technology. His areas of expertise are high-speed VLSI signal processing, image processing and compression, full-custom and low power circuit and architecture design, adaptive filtering, Gigabit Ethernet transceiver design, high-density deep sub-micron CMOS design, high temperature superconductors, and biomedical electronics. He has published nearly 50 papers in his areas of expertise and holds 26 patents with several patents pending. He is an IEEE Fellow and received his Fellow award for his contribution to the design of high-performance digital signal processors. He has participated in numerous national and international conferences and other professional activities in his field as an organizer, session chair, panelist, invited lecturer, and moderator.

Memory sub-system Advances and Trends
Track Chairman: Dr. Raman Menon Unnikrishnan. Dean of the College of Engineering and Computer Science, California State University, Fullerton 

Dr. Raman Menon Unnikrishnan is Professor of Electrical Engineering and Dean of the College of Engineering and Computer Science. He is active in teaching and research in the areas of Control Systems, Power Electronics, and Signal Processing and is an author of numerous research papers and presentations in these areas. He has been a consultant to several industries and governmental agencies and has been involved in technical and professional education for industries. He is active nationally in the field of Engineering Education and Engineering Accreditation. Prior to joining Cal State Fullerton, Dr. Unnikrishnan was on the faculty of the Rochester Institute of Technology in Rochester, New York, where he also served as Associate Dean for Graduate Studies and Research for the College of Engineering from 1989 to 1991 and as the Head of the Electrical Engineering Department from 1991 to 2001. He received his BS degree from the University of Kerala, India, his MS from South Dakota State University, and his Ph.D. degree from the University of Missouri, all in electrical engineering.  Dr. Unnikrishnan is a member of Eta Kappa Nu, Tau Beta Pi, ASEE, and a Senior Member of IEEE.

1:30 pm - 2:00 pm

Keynote

"Toward Low-Power and High-Speed Memory-Based Computing Chips"

Low-power and high-speed computing issues are described based on truly memory-based chips thinking of power consumption and architecture.

Tadao Nakamura received his PhD in Electronics using Computer Aided Design in 1972 from Tohoku University. Dr. Nakamura is currently a Professor of the Department of Computer and Mathematical Sciences at Tohoku University. He was founding chair of the department in 1993. Prior to that he was a Professor of the Department of Mechanical (Machine Intelligence and Systems) Engineering at Tohoku University and a Visiting Lecturer in the Department of Information Science at the University of Tokyo. From 1994-98 he was a Visiting Professor of Electrical Engineering at Stanford University. His recent research interests are in computer architecture, especially pipelining based microarchitecture, and low power concepts in chips, in general. He was elected in 2004 to receive the IEEE Computer Society Taylor L. Booth Award. He has been Organizing Committee Chair of the IEEE COOL Chips conference series fully sponsored by the IEEE Computer Society. He was also a Program Committee member of the IEEE HOT Chips 15. Dr. Nakamura was elected Fellow of the IEEE in 2002 for contributions to pipelined computer architecture and computer engineering education.

Dr. Pierre Fazan, Founder and CTO, Innovative Silicon.
 

"How to Cut Die Cost in Half"

Effectively managing die size is an important consideration for System on Chip (SoC) designers, and the function that consumes the most silicon is memory. The requirement for large and increasing amounts of embedded memory has become a key factor in SoC design, and an important consideration for designers looking to minimize their die costs. As such, there is a large market for an ultra-dense memory technology, particularly for designs produced at the 90 nanometer and smaller nodes.  This presentation will discuss how designers can dramatically cut their die costs by harnessing the unique capabilities of silicon-on-insulator (SOI) devices, which can be used to store data at double the density of embedded DRAM. The presentation will include a discussion of the performance, energy consumption, manufacturability, and scalability of this new technology compared to existing embedded DRAM and SRAM. In addition, we’ll discuss the different floating body memory architectures and describe how solutions can be optimized for speed, power, and cost.

Dr. Pierre C. Fazan was born in Lausanne, Switzerland where he obtained his Physics diploma and Ph.D. degrees at the Swiss Federal Institute of Technology (EPFL) in 1984 and 1988 respectively.  From 1989 to 1997 he worked as process integration engineer then manager at Micron Technology, Boise USA, focusing on DRAM process integration. In 1997 he was named Professor at the Swiss Federal Institute of Technology, Lausanne, EPFL, where he taught in the field of IC manufacturing.  In 2002 he co-founded Innovative Silicon, developing a new SOI single transistor memory technology. This company was funded in December 2003. He acted first as CEO and is currently CTO of Innovative Silicon. He has authored or co-authored more than 100 papers and invented or co-invented more than 150 US patents. Dr. Fazan has served as member in program committees of the SOI Conference, IEDM, VLSI Tech. Symp, ISIF, ESSDERC, INFOS and ECS Conferences.

Kyle Kirby, Engineering Manager --The 3D Stacking Development Team,  Micron Technologies.
 

"Osmium Packaging Technology"

Micron's Osmium packaging technology, which borrows its name from one of the densest natural elements known to mankind, is poised to drive semiconductor packaging to the wafer level. Conventional packaging methods are reaching their technological limits, and electronics manufacturers are still demanding smaller, denser packages, improved performance, and lower system costs. Micron's Osmium packaging technology, with its potential to deliver extremely high-density, small-form-factor solutions, is the right technology at the right time. Osmium technology combines through-wafer interconnects, a redistribution layer, and wafer-level encapsulation—along with hundreds of supporting US patents and process engineering breakthroughs—and effectively extends the fabrication process to finished goods. This unique blend of leading wafer-level packaging technologies and IP promises to change the dynamics of semiconductor manufacturing and set a new standard for semiconductor packaging.

Kyle Kirby graduated in 1993 from Northern California's Humboldt State University with a Bachelor of Science in Industrial Technology. He joined Micron in 1994 pursuing a Manufacturing Engineer career, but ended up as a Technologist in the Research and Development department. He currently holds 20 US Patents with nearly 50 more in process at the USPTO. He has been with the Micron Advanced Packaging R&D group since its' inception and is currently Engineering Manager of the 3D stacking development team.
 

Network-on-Chip (NoC) Architectures for Complex SoCs

Track Chairman: Dr. Goran Matijasevic, Director of Research Development, The Henry Samueli School of Engineering, University of California, Irvine

Dr. Goran Matijasevic, Director of Research Development, The Henry Samueli School of Engineering, University of California, Irvine.

Track Chairman

Dr. Goran Matijasevic is Director of Research Development at The Henry Sameli School of Engineering at UC Irvine. In this capacity, he works on formation of new industry-university and academic collaborations, especially focusing on new interdisciplinary research initiatives. Prior to this, he was the Research Coordinator of the Integrated Nanosystems Research Facility at UC Irvine, where he worked closely with industry partners on making them aware of available university resources. Prior to UCI, he worked as a senior engineer at QPlus, a telecommunications start-up company. From 1994 to 2001, he was at Ormet Technologies, where as Director of Research he was working on development of polymer and metal materials and structures for electrical interconnect of high density circuits, new metal alloys for use in conductive adhesives, materials for embedded passive components and heat sensors, and high thermal efficiency electronic substrates. ¨He managed multiple SBIR projects that led to several industry consortia projects, as well as a license agreement with a Fortune 100 company. He has 4 U.S. patents, 3 book chapters, and over 40 conference and journal publications and has served on the NEMI Industry Roadmap committee. He served as NanoWorld Conference Technical Chair, the Electronic Components and Technology Conference (ECTC) Interconnect Chair and Emerging Technologies Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing Committee. He is currently on the OCTANe (Orange County Technology Action Network) Operations Committee. Goran received his PhD from UC Irvine in Electrical and Computer Engineering and his MBA from Pepperdine University. He is also a member of the TriTech Advisory Board, Tech Coast Venture Network, Life Sciences Industry Council (LINC), IEEE, and ASME.

"Exploiting Interconnect-Centric Structural Regularity for Cost-Efficient SoC Design"

In this presentation we examine existing efforts towards bridging the SoC design gap between electronic design automation tools and deep submicron silicon technologies for building next generation, heterogeneous multiprocessor SoCs. We claim that cross fertilization from multidisciplinary domains, such as design for manufacturing, IC design flow based on regular fabrics, system-level IP reuse, parallel and distributed processing, computer networks, operating systems and software architectures together with a strive for regularity may lead to innovative design techniques that would improve productivity of complex cost-efficient SoCs. Focusing on a modern packet-switched network-on-chip implementation, we explore structural regularity in technological, architectural, topological, algorithmic and application features that simplify interconnect and network interface realization and improve system concurrency using efficient routing, intensive communication and synchronization algorithms. By embedding multi-dimensional regularity mechanisms within application domain-specific design paradigms and tools we can enable full-scale integration of complex multiprocessor SoCs with increased design complexity and growing variability. These SoC architectures will scale at 45 nm and below by using an interconnect-centric network-on-chip design methodology with a regular fabric that will also help resolve manufacturing problems and provide higher yields.

Marcello Coppola received the Laurea degree in computer science from Pisa University, in 1992. Previously, he was with the Transputer architecture group at the INMOS in Bristol (UK) working on the architecture of the C104 router. He is now head of the Grenoble Research Laboratory of “Advanced System Technology”, a corporate research organization within ST Microelectronics, and currently responsible for the STNoC project. His main duties are budget management, coordination of several external research groups and open communication through technical articles, ST press announcements, etc. His research interests include design methodologies for system-on-chip, with particular emphasis to network-on-chip, MPSoC architecture, program modeling and system level design. His research focuses discrete-event simulation, real-time operating systems, system-on-chip modeling, SoC architecture and on-chip communication networks. He has published research articles in various books and journals. He was a member of the OSCI language working group contributing towards SystemC2.0 definition and OSCI standardization. He has been chair of many international conferences on SoC design and has helped in organizing several others. He has been a program committee member of DATE, FDL, CODES+ISSS and DAC and has contributed to the MEDEA+ EDA Roadmap, as well as the SystemC standardization.

Jeff Haight, Director Technical Marketing & Zainab Al-Shamma, Field Applications Engineer. SONICS Inc.

"Abstraction Levels for SoC Memory Subsystem Design with MemMax."

The sheer complexity of present day System-on-Chips (SoCs) requires designers to make implementation decisions at multiple abstraction levels in order to optimize the overall architecture of the SoC. Analogous to the multiple abstraction level of multi-core SOC interconnects and processors, there is a need to have similar abstraction levels of the memory subsystem for an intelligent system-level view to enable more efficient scheduling and better Quality of Service (QoS) for the different cores. Flexibility of the abstraction levels in a memory subsystem is key to tailoring enhanced memory utilization for the various applications, and is essential to optimal performance in systems with heterogeneous requirements (different speeds, endianess, QoS, security requirements, etc.), e.g., involving bursty H.264 / DVB video. The Sonics MemMax IP, an intelligent memory scheduler, provides tuning capabilities that leverages the states of both the physical memory sub-system (memory and memory controller) and the system-level processors for optimized traffic management and efficient memory utilization. Sonics MemMax allows the SoC integrator to easily balance the trade-offs between area, performance, and power for overall system efficiency and robustness.

Jeff Haight:  Jeff is currently the Director of Technical Marketing for Sonics, Inc., the leader in IP generation for high performance SoC interconnects. He has been in the electronics industry for over 3o years, having participated in communications and RADAR signal processing system design and design management, and various technical marketing, business development, and engineering management roles in semiconductors, CAD development, and IP marketing at LinkaBit, TSC, TRW, Zoran, VLSI, Compass Design Automation, and Toshiba. He has published over 25 articles and conference papers. Jeff enjoys reading, tennis, skiing, and music in his not-so-copious free time and when not chauffeuring his two teenagers to or from some destination.

Zainab Al-Shamma:  Zainab is currently a field applications engineer at Sonics, Inc.; responsible for creating evaluation demos and training materials to help customers use Sonics products most effectively. She also worked as a design services engineer for the company, helping to design a customized crossbar and helping to integrate and optimize the SonicsMX® interconnect into customer’s complex SoC designs. Previously, Zainab was a member of the technical staff in ASIC development at Luminous Networks and at Silicon Graphics, and she served as an intern at IBM/Somerset Design Center and STAR Laboratories at Stanford University. She is proficient in a number of industry software tools including Verilog, Synopsys, Verisity and Magma. Zainab holds a B.S. degree in Electrical Engineering from Stanford University.

Dr.

"Design and Analysis of A Network-on-Chip (NoC) Processor Architecture"

In this talk I will present our work on the design and modeling of a NoC based architecture called MaRS. The work covers system level modeling and performance evaluation of the proposed architecture for high performance and low power applications in communication and multimedia processing.

Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor.   Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing.  His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications.  The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing.  DARPA and NSF fund the MorphoSys project (total support $1.5 million).  Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine.  Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS).  Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin.  As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms.  He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years.  He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.

Dr.

"Communication Analysis of the Cell Broadband Engine Processor"

 The existence of major obstacles to the traditional path to processor performance improvement has led chip manufacturers to consider multi-core designs. These architectural solutions promise a variety of power/performance and area/performance benefits. But additional care must be taken to ensure that these benefits are not lost due to inadequate design of the on-chip communication network.   This paper presents the design challenges of the on-chip network of the Cell Broadband Engine (Cell BE) processor, and describes in detail its architectural design and the network, communication and synchronization protocols. In the experimental evaluation, performed on an early prototype, we analyze the communication characteristics of the Cell BE processor, using a series of microbenchmarks involving various DMA traffic patterns and synchronization protocols. We find that the on-chip communication subsystem is well matched to the to computational capacity of the processor. A Synergistic Processing Element (SPE) can issue an internal direct memory access (DMA) operation in less than 4 nanoseconds, and a DMA of a single cache line can be executed in less the than 100 nanoseconds. SPEs can achieve the optimal bandwidth of 25.6 GB/second in point to point communication with surprisingly small messages -only a few KB, using batches of non-blocking DMAs. The aggregate network behavior under heavy load is also remarkably efficient, reaching almost 200 GB/second with collective patterns and optimal contention resolution under hot-spot traffic.

Fabrizio Petrini is a laboratory fellow in the Applied Computer Science Group in the Computational Sciences and Mathematics Division at Pacific Northwest National Laboratory (PNL). Before his appointment at PNL, he was a member of the technical staff of the CCS3 group of the Los Alamos National Laboratory (LANL), a research fellow of the Computing Laboratory of the Oxford University (UK), a postdoctoral researcher of the University of California at Berkeley, and a member of the technical staff of the Hewlett Packard Laboratories. His research interests include various aspects of supercomputers, including high-performance interconnection networks and network interfaces, fault-tolerance, job scheduling algorithms, parallel architectures, operating systems and parallel programming languages. He received numerous awards from the Derpartment of Energy (DOE) for contributions to supercomputing projects, and from other organizations for scientific publications.

  5:15 pm - 6:15 pm

Panel:  Architectural and Performance-Related Challenges for Complex SoCs

Moderator:  Ron Wilson, Executive Editor, EDN Worldwide.
 

Ron Wilson, Executive Editor, EDN Worldwide.

Moderator

Ron Wilson, EDN's executive editor, boasts a checkered career reaching back to the dawn of medium-scale integration, whatever that was. As a design engineer for Tektronix, Inc. he developed bus interfaces and participated in processor- and graphics-engine architecture and design, as well as evaluation engineering and software-driver development. The most tangible project in which he participated led to—arguably—the first engineering workstation, unknown today except for its minor supporting role in the original Battlestar Galactica television series.

Later an exile from engineering, Ron wandered through the realms of training and marketing before landing happily in the editorial world, first with Computer Design Magazine in the mid-1980s. From there he moved to CMP Media, where he wrote for EE Times and was briefly involved with ISD Magazine. His primary interests are system design based on highly-integrated ICs, the interaction of chip and software engineering and the future of design practice in the increasingly global electronics community.
 

Dr. Marco Racanelli, Vice President of Technology and Engineering, Jazz Semiconductor.

Panelist

Dr. Marco Racanelli is the Vice President of Technology and Engineering at Jazz Semiconductor, an independent pure-play wafer foundry focused primarily on specialty CMOS process technologies optimized for the manufacture of highly integrated analog and mixed-signal semiconductor devices. His responsibilities include leading technology development, modeling, design automation and design service teams.  Before joining Jazz in 2002, Dr. Racanelli held technology and engineering positions at Conexant Systems. He also held management positions with Rockwell Semiconductor Systems prior to the Conexant spin-off in January 1999. He joined Rockwell in 1996 and has since held several posts of increasing responsibility in the area of technology development.  In these positions, Dr. Racanelli helped establish industry leadership in SiGe and BiCMOS technology, and was instrumental in building a strong design support organization for Jazz Semiconductor. Prior to joining Rockwell, Dr. Racanelli worked at Motorola, Inc., where he contributed to bipolar, SiGe and SOI development for Motorola’s Semiconductor Products Sector. He has authored or co-authored more than 50 technical publications and holds 30 U.S. patents.  Dr. Racanelli received his Ph.D. and M.S. degrees in Electrical and Computer Engineering from Carnegie Mellon University, and his B.S. degree in Electrical Engineering from Lehigh University.

David Fritz, Chief Executive Officer,  Silistix, INC.

Panelist

David Fritz is Chief Executive Officer of Silistix, the worlds first clock-less on-chip interconnect company. Prior to joining Silistix, Fritz was vice president of marketing and business development for ARC International. He was the founder and president of Production Languages Corporation, a pioneer in configurable processor technology, where he was awarded a U.S. patent covering fundamental processes related to configurable processors. In 1999, ZILOG acquired Production Languages, naming Fritz the vice president of ZiLOG’s Advanced Cores R & D as well as vice president of ZiLOG’s Development Systems Group. Fritz holds degrees in Mathematics and Computer Science from Manchester College.

Larry Morrell, Vice President of IP Products, Impinj Inc.

Panelist

Larry Morrell has over 20 years of semiconductor-industry experience in engineering, management, and marketing roles. He directed marketing at Cypress for their programmable clocks division and market-leading USB chips. Prior to that he was the Vice President of Marketing and Business Development for Data I/O where he helped popularize FPGAs and co-founded an industry trade show. Earlier in his career he established a European sales and marketing operation in Paris for an IC startup called Seattle Silicon and worked in engineering and management at Boeing. Mr. Morrell earned a B.S. in Computer and Electrical Engineering and a B.A. in Russian Languages from New Mexico State University.

Bill Chown, Director of Engineering, Mentor Graphics. Representing SPIRIT Consortium.

Panelist

Bill Chown, currently a product group director for the system-level engineering division at Mentor Graphics, moved to the semiconductor industry with Intersil Semiconductors, where he went from designing mixed signal and DSP systems, at chip and board level in the UK, to managing projects through to layout and production test. He subsequently worked in EDA and test software development in Europe and the US with Mentor Graphics, Summit Design/TSSI, Integrated Measurement Systems and Credence. A twenty-five year veteran, Bill currently specializes in TLM and RTL platform-based design and verification. He has been involved with standards activities for several years, serving in the CFI, ECSI, and STIL initiatives, is past chair of the TTTC TAC on Virtual Test, is currently a member of the STIL working group, and is a board member for The SPIRIT Consortium and for OMG. Bill earned an Electronic Engineering degree from the University of Wales and an MBA from the University of Oregon.

Paolo Cocchiglia,  Vice President, ADS (ASIC Design and Security)
Infineon Technologies North America Corp.

Panelist

Paolo Cocchiglia is currently Vice President of the ADS (ASIC Design and Security) business group at Infineon Technologies North America Corp. Prior to joining Infineon, from 1993 till 2003, Cocchiglia held various managerial positions at ST Microelectronics, both in Italy as well as in San Jose, Calif. He was program manager at ST Microelectronics in Italy, then assumed Business Development Engineering, Product Marketing and Strategic Marketing Director positions in the San Jose office. Cocchiglia’s other professional experience consists of positions at Seleco and Fontilevissima, where he held consultant positions, and Venture, where he was Design Engineer. He holds an MBA from Profingest Management School in Bologna, Italy, and an Electronic Engineering degree from Padua University, Italy.

Panel: Architectural and Performance-Related Challenges for Complex SoCs  

Moderator: Ron Wilson, Executive Editor, EDN Worldwide.

Panelists:

1. Mohy Abdelgany, President and Chief Executive Officer, Newport Media , Inc.

2. David Fritz, Chief Executive Officer, Silistix, Inc.

3. Larry Morrell, Vice President of IP Products, Impinj Inc.

4. Bill Chown, Director of Engineering, Mentor Graphics. Representing SPIRIT Consortium.

5. Paolo Cocchiglia, Vice President, ADS (ASIC Design and Security) Infineon Technologies North America Corp.

 Conference Exhibit & Reception Open

Detailed Program Information (abstracts & bios) for Thursday, November 2, 2006*

  8:00 am - 8:15 am

Farhad Mafie, President and CEO of Savant Company Inc.

"Welcome and Opening Remarks and Conference updates"

Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models.

Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis.  He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company.  

Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.

His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies.  

Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

  8:15 am - 12:00 pm

Semiconductor Trends and New Design Approaches for Complex SoCs

Track Chairman: Farhad Mafie, Savant Company Inc.

"HardCopy Structured ASICs A Superior Design Flow."

A Superior Design Flow Many designers face a dilemma at the beginning of a project. They can either create innovative products fast using expensive FPGAs, or use a long, effort-intensive standard cell ASIC design flow to target the lowest possible cost.
Some companies try to do both by designing twice – once for an FPGA prototype and another for the low cost ASIC. The result can be a very expensive process with little chance of reducing the development risk.  The best of all worlds is a design environment that supports FPGA development and seamless migration to a low cost ASIC solution. The combination allows companies to generate breakthrough designs, test them in the market, add features and functions in real time to respond to industry demands, then produce a single product that supports a wide range of market segments. Alternatively, they can generate several variations each of which support a single market or application. If designs prove popular, companies can migrate them easily to a high-volume, low-cost structured ASIC with no disruption of deliveries. Now companies can get the performance they need for today’s designs and get them to market in a low risk, cost effective process. Companies can take advantage of Altera’s HardCopy II structured ASIC family that supports about 3.6M ASIC gates and 8.8M RAM bits, running over 350 MHz performance. Once the design is fully verified in the FPGA, the designer can submit it to Altera’s HardCopy Design Center, and receive HardCopy II prototype devices within 10 weeks. HardCopy II devices require 50-70% lower power than an FPGA, which also means lower cost for such items as cooling fans and heat sinks. Altera provides that best-of-all-worlds solution and companies are employing the new alternatives it offers for both OEM systems and for ASSP development.

Francis Chow is a business development manager at Altera and has extensive experience in the semiconductor and electronic design automation (EDA) tools industries. At work, he is responsible for identifying and evaluating semiconductor and EDA startups for M&A, equity investment and partnership opportunities. Before Altera, Francis led a design team at Texas Instruments’ Broadband Communications Group on DSL and VoP chipsets. During his tenure, TI achieved #1 market share position in both DSL and VoP markets. Francis received his BSEE from Rensselaer Polytechnic Institute and his MSEE from University of California at Berkeley. He is currently pursuing his MBA at Haas School of Business, University of California at Berkeley, on a part-time basis.

"Pre-Mature Claims to Structured ASIC Demise"

The death of the structured ASIC has been greatly over exaggerated and is not imminent. In fact structured ASIC technology is evolving into a semiconductor product that fits, exceedingly well, into specific market niches. With all of the negative press surrounding structured ASICs, recently, it is easy to understand how people can come to the conclusion that structured ASIC technology is dying. However, this paper will explore the problems seen so far with structured ASIC products; compare and contrast structured ASICs with their semiconductor counterparts; and finally explain why structured ASICs are here to stay and where they fit within the current market space. Outline:
I. Introduction, II. Exploring the Issues Surrounding Structured ASIC Products, III. Comparing Different Technologies (SA vs. SC vs. ASSP),  IV. Examining the Structured ASIC Market (A. Mid-range ASIC market, B. FPGA conversion market), V. Conclusion.


Rick Mosher has more than ten years of engineering experience managing the design, verification and integration of complex digital logic blocks used to facilitate and enable multi-million dollar digital products.  With a focus on FPGA, ASIC and PCB design coupled with product management and strategic marketing, Mosher possesses the skills necessary to aid AMI Semiconductor in developing digital IP roadmaps, analyzing market data and providing customer support for the Structured Digital Product business unit. Prior to his role as product manager at AMI Semiconductor, Mosher was a senior member of the design team responsible for the development of digital hardware used to enable TDMA and CDMA wireless systems for Nortel Networks. During his tenure at Nortel, Mosher was responsible for FPGA, ASIC and PCB design. Additionally, Mosher was the verification prime on the team, responsible for the system level verification of multi-million gate ASIC designs.  A published writer and expert speaker, Mosher’s education has been focused on telecom and computer engineering.  

Gordon Mortensen, Engineering Director - Advanced Power, National Semiconductor

"Low Power SoC Design Using Multiple Voltage Islands and Adaptive Voltage Scaling"

SoC architectures with multiple voltage islands and the application of Adaptive Voltage Scaling (AVS) can greatly reduce power consumption and improve energy efficiency in SoC designs. This discussion/paper will present simulated and measured power savings with AVS and investigate voltage island partitioning options for low power SoC design.

Gordon Mortensen is an Engineering Director in the Advanced Power Group at National Semiconductor. He has 23 years of experience in the semiconductor industry in engineering management, as a design engineer, and as a product engineer. Gordon's embedded systems experience includes 4 bit, 8 bit and 16 bit micro-controller products, x86 platform chipsets and PowerWise(R) Portable Power Management products.

10:00 am - 10:30 am

Keynote

"Lessons learned at 65nm that will be applied to 45nm"

TAs 65-nanometer process technology pushes the power/performance curve, the economics of volume production come into play as critical element in semiconductor chip design and manufacturing. The upfront costs to begin the design cycle have skyrocketed such that customers must be able to see their product into high volume production quickly. To allow customers to amortize those initial costs and see a sizable return on their investment, the whole semiconductor foundry ecosystem – from DFM design firms to the manufacturing companies – needs to remain on the same roadmap. Semiconductor foundry companies can’t operate in a vacuum. At advanced technology nodes such as 65nm and sub-65nm, the design complexity demands that the foundry have the design and manufacturing expertise of an IDM mixed with the services of a pure-play. With 65nm becoming more mainstream, the industry will take the lessons learned and apply those 45nm. Consumer electronics and high-speed computing/networking will be the beneficiaries of the advanced process technology work being done now. This keynote address will focus on the following:

1-Business/economic trends for those customers looking to engage in a 65nm chip design;
2-The need for the foundry ecosystem to stay on the same roadmap and provide an open platform for customers; and,
3-Lessons learned at 65nm that will be applied to 45nm.

Ana Molnar Hunter is vice president of Technology for Samsung Semiconductor, Inc.’s System LSI foundry business. Leading the US business development team, Hunter is responsible for Samsung’s foundry customer activities in North America. She is also responsible for setting the strategic development direction of the North America foundry business. Prior to joining Samsung, Ms. Hunter spent the last 15 years working in the semiconductor foundry industry in various positions as a consultant, vice president of U.S. operations for Communicant Semiconductor Technologies AG, Germany, and vice president of EDA and customer services for Chartered Semiconductor, Inc. She holds a B.S. in chemistry from Duke University.

Ray Abrishami, Senior Director of Wireless Business Group, Fujitsu Microelectronics America, Inc.

"CMOS, Scaling, and the Future CMOS Scaling. Has it bottomed out?"

Scaling, one of the most pivotal transformations in the silicon technology occurred in such an unglamorous, subtle, persistent and gradual manner, that the technology genius behind it never received the accolades it so richly deserves. For some decades now, we have relegated the silicon scaling to somewhat routine factory automation and manufacturing evolution, taking it for granted, and thinking of it as an endless path for further leveraging the silicon technology. Scaling concept was a result of a quest for cost and performance optimization. This marvel of a technological endeavor has been singularly responsible for providing affordable portable electronic equipment to the consumers, delivering such astonishing level of functional complexity and performance that was unimaginable a relatively short time ago. The key questions before us now are: has the technology scaling bottomed out? And how much longer can we continue on the scaling path? These are intriguing questions that are worth exploring as we embark on introducing the 65 nm technology node and beyond. At its inception, it was clear that CMOS would be an ideal technology for scaling. Providing a relatively simple basic switch structure initially facilitated an ad-hoc selective two dimensional scaling, soon to be followed by three dimensional scaling of geometries and design rules. Earlier predictions warned about runaway power dissipation as functional density and frequency of operation increased. As time has shown, we were able to achieve close to full scaling of the technology which included scaling down the power supply (vdd). In addition, deployment of new design methodologies for power and clock distribution/ management coupled with proper use of asynchronous design techniques and availability of innovative packaging technologies have allowed us to pack tens of millions of devices on a single piece of silicon for operation at gigahertz (and higher) clock rates.  While we recognize that there are theoretical as well as practical limits to scaling, at the same time such challenges present new opportunities which would enable us to achieve the levels of integration up to billion devices (gigascale) or even to contemplate designing and building chips with trillion devices (terascale). Contemplating such possibilities would make CMOS scaling seem endless. However, the notion of scaling as we know it today will change to a higher plateau of sophistication and complexity even before we reach the fundamental physical limits. A few examples follow:

The future CMOS scaling must overcome many challenges. As dimensions get smaller and smaller, we must find ways to reliably transfer component images onto the wafer. At the fabrication level, equipment precision and control will become ever increasingly more important. Shallow junctions and highly scaled down dimensions will force atomic-level manipulation of the implant materials. With increase in speed (clock rate), power dissipation, chip density, and current density, the reliability concerns (oxide, hot-carrier, metallization,…) will also grow. The demand to further lowering of the transistor Vt will exacerbate the sub-threshold leakage current. Bulk punchthrough, impact ionization breakdown, gate-induced leakage current (caused by a tunneling phenomenon). While lowering of Vdd will help in many ways, it cannot be considered a solution. These problems and concerns are not new and have been with us for many years. We have done a great deal to reduce their impact. However, as we continue on this path, it is more than likely that these problems will return as stronger impediments to silicon integration. Ultimately, we will reach a point of having to deal with the basic limits of systems and material based on the laws of physics. For example, the minimum energy transfer necessary for a binary switching operation has a finite limit. This energy [ f(kt) ] is independent of the material, device or circuit used to build the switch. While the basic physical limits seem to warn us about the presence of a metaphoric “wall” out there, at the same time such challenges encourage tireless effort by many to change the paradigm of analysis and comparison and invent new and, for sure, disruptive process technologies and compounds that will help push the ”wall” out even farther. At the end one, more or less, definitive conclusion can be reached. Technology scaling has not bottomed out. It will continue, but we will for certain, before long, be using new base technologies, material and possibly device constructs.

Ray Abrishami is currently the Senior Director of SoC Engineering and Marketing at Fujitsu Microelectronics America, Inc. (FMA). His responsibilities include product marketing for FMA and SoC development for specific vertical markets such as WiMAX-compliant broadband wireless, VoIP and biometric sensor products. He also oversees the development of FMA solution platforms for SoC involving IP development, acquisition and integration with processor cores and peripheral sub-systems as part of the IPWare™ SoC program.  Before joining Fujitsu, Abrishami worked at LSI Logic Corporation where he held various senior engineering management positions in the ASIC Division. His responsibilities included design methodology development, cell architecture, circuit design and design library development functions. He also had engineering management responsibility for the development and delivery of several generations of sub-micron technology products. Abrishami has been closely involved in the definition and development of SoC, intellectual property, top-down VLSI design methodologies and automation tools in the areas of front-end design, physical design and test/testability. Prior to joining LSI Logic, Abrishami held the highest-level engineering and general management positions at Data General Corporation‘s Semiconductor Division where he directed the VLSI system development groups. He led the development and release of VLSI chip sets for three generations of computer systems.  Abrishami represented LSI in the Semiconductor Research Corporation’s (SRC) Design Sciences Technical Advisory Board. He was chairman of SRC's Design Sciences Technical Advisory Board in 1996. From 1994-1997, Abrishami was also a member of the Design and Test Technical Working Group (TWG), responsible for the development of the National Technology Roadmap for Semiconductors.  Abrishami holds bachelor’s and master’s degrees in electrical engineering from San Jose State University. He participated in Stanford University’s engineering management program, and is a member of IEEE, Tau Beta Pi and Eta Kappa Nu. He has been granted three U.S. patents in circuits and systems.

"Ultra Low-Power Memory IPs for SoC Designs"

Cyrus Afghahi, PhD - CEO & Co-Founder Cyrus Afghahi is a semiconductor industry professional with a successful track record of leading technology based organizations. Prior to co-founding Novelics in 2005, he was Technical Director for the Office of the CTO at Broadcom Corporation. He has over 20 years experience leading strategic technology initiatives in low power and high speed VLSI designs for advanced, high performance applications. Prior to joining Broadcom, Mr. Afghahi has held key technical and management positions at Intel Corporation, Ericson Radio and Carlsted. He received his PhD in Linkoping, Sweden in 1985. He holds more than 60 patents.
 

Syed B. Huq, Hardware Engineering Manager, Cisco Systems, Inc.

"SerDes Modeling Challenges in complex SoC and Solutions using IBISv4.1"

Need for higher bandwidth in complex SoC designs has pushed various market segments to move quickly to Serializer-Deserializer (SerDes) type of I/O architecture. These are evident in standards such as PCI-Express, SATA, XAUI, CEI and more. While the I/O solutions in SoC designs attempt to solve the high bandwidth requirements, the ability for Signal Integrity Engineers to model such an I/O has remained an ever challenging dilemma.   Today HSPICE, Matlab and various home grown methodologies provides some level of solution but fails to solve many Signal Integrity simulation issues since there are no easy linkage to the PCB environment. Many such temporary partial solutions in SoC designs are proprietary in nature and customers are unable to simulate Vendor-A’s silicon with Vendor B’s silicon. The IBIS (I/O Buffer Information Specification) committee has taken this challenge and now supports a multi-lingual language where hooks are placed within the IBIS model to use VHDL-AMS as a language to model complex SerDes structures. This provides a way for SI tools to put together a simulation topology where 100s of SerDes links in SoC designs can be simulated without any compromise in run-time using IBISv4.1 models.  This paper will show the advantage of IBISv4.1 over HSPICE and other modeling schemes and the path toward a solvable high speed modeling challenge for many SoC designs. Interconnect modeling of various structures within IBIS using ICM will also be shared since all of these components are needed for a full system level topology for SerDes simulations.

Syed B. Huq is a Senior Hardware Engineering Manager at Cisco Systems, Inc. For the past 7+ years, Syed has been responsible for all of the ASIC Signal Integrity and Packaging Design requirements for ASICs and FPGAs in the ISBU, DCBU business groups in Cisco Systems, Inc.. Syed also drives various methodology requirements across Cisco Systems, Inc. and provides Modeling and Library solutions in High-Speed I/O and interconnect areas. Syed is also the Vice-Chair of ANSI/EIA-656A(IBIS) where user requirements are driven to solve complex modeling challenges. Syed holds a BSEE from Southern Illinois University (SIU-C) and a Telecommunication Engineering certificate degree from UC Berkeley extension. 

  1:00 pm - 1:30 pm

Keynote

Keynote: "Avoiding the Death of The SoC Venture, A New Player is Born".

With exploding NRE costs, increasing technology and market uncertainties, and standard and programmable products squeezing available markets, investing in a leading-edge System-On-Chip venture has become an adventure that few capitalists are willing to stomach. Required returns and volumes are exploding. Two trends however are mitigating this trend:
verticalization and collaboration. Vertical markets applications will be increasingly enabled and become industry and technology drivers, and the SoC process will be globally optimized via the collaboration of multiple players that consolidate multiple tasks in an accelerator-based open platform. Capitalist funding in Virtual-SoC Ventures (VSCs) with small "SoC-Lite" teams will explode, leveraging radical outsourcing and aggressive vertical specialization to expand investment return while mitigating risk. These new ventures can guarantee industry replenishment while about a third of industry players may disappear next decade. The death of the SoC may be a myth.

Juan-Antonio Carballo is IBM Corporation's Venture Capital Executive for Semiconductors and Hardware Systems, responsible for creating and managing strategic projects with top-tier Venture Capital firms and their portfolio companies. Prior to this role, Juan-Antonio was leading research in adaptive communications chips at IBM Research. He won an IBM Research Division award for his work in this area. He filed 23 patents and has over 20 publications in low-power design, communications systems, design economics, and electronic design management. He is the Chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers Chapters, the Chair Elect of IEEE's DATC Committee, and VSIA's R&D Chair in 2004-5. He has been on the committee of six symposiums and conferences, and was the General Chair for Electronic Design Processes
2004 in Monterey, CA. His prior work experience includes stays at Digital Equipment (currently HP) and LSI Logic. Juan-Antonio holds a Ph.D. in Electrical Engineering from the University of Michigan, an M.B.A. from the College des Ingenieurs (Paris), and a M.Sc. in Telecommunications Engineering from the Universidad Politecnica de Madrid.

  1:30 pm - 5:15 pm

EDA Tools and Design Methodologies for Complex SoCs

Track Chairman: Dave Bursky, Semiconductor Editor, EETimes Magazine

Steve Carlson, Vice President, Cadence Synthesis Team

"The Quiet Revolution"

Predictability, power, and complexity have driven major retooling of design automation technology and methodology twice over the past decade in the so called back-end implementation process. However the established practices in front-end have been resilient, even resistant, to such transformations. That is about to change. This session will examine the cumulative effects of a decade of progress and innovation that has surrounded the front-end design space, but is only now starting to create a compelling need for change.

Steve is a Vice President on the Cadence Synthesis team.  In that role he is focused on marketing the solution for the best Quality-of-Silicon (chip speed, area, power, test measured after wires).  Carlson reports to Chi-Ping Hsu, Corporate VP for New Synthesis at Cadence.  Steve joined Cadence in April in 2003 via the Get2Chip acquisition, where he was the VP of Marketing.  Prior to Get2Chip, Steve was the CEO of Tharas Systems, a hardware acceleration company.  Steve has also held various management positions at Escalade, LSI Logic, United Technologies and Synopsys.  At Synopsys, Steve was a part of the original Design Compiler technical team responsible for timing analysis and optimization.  Steve was the author of the industry’s first book on high-level design: Introduction to HDL-based Design Using VHDL.  Steve has a BSEE, a BSCS, and an MSEE, all from the University of Colorado.

John Gallagher, Senior Director ASIC Synthesis Marketing, Synplicity, Inc.

"What’s Up? Growth Areas in the Electronics Industry"

Cell-based ASICs have been in decline and are likely to continue so, for both economic and technical reasons. However, not all areas of custom IC design are down - changing conditions in the semiconductor and electronics industries provide new opportunities for innovation in programmable devices and structured/platform ASICs. The rapidly growing importance and increasingly diverse application of FPGAs and the rise of structured ASICs has caused significant changes in the design flows, software tools, and engineering skill-set required by companies developing electronic systems and IP. Examples of growth drivers include DSP content in FPGAs, ASIC/System prototyping with FPGAs, and “derivative” product development with Structured/Platform ASIC. Synplicity believes that these growing areas provide an opportunity to benefit from this historic transition in the semiconductor industry.  In his presentation, Mr. John Gallagher will discuss the several growth areas in the semiconductor industry and the impact these are having on silicon and EDA vendors as they adapt to the inherent challenges of this changing industry.

John Gallagher is the Senior Director of ASIC Synthesis Marketing at Synplicity, Inc. Mr. Gallagher holds a B.S. in Materials Science and Engineering and an MBA from Cornell University. Prior to joining Synplicity in 1999, he served as director of place and route marketing at Cadence Design Systems. He has also held ASIC marketing and engineering positions at LSI Logic Corporation and Hewlett Packard Company.

Dr. Carl Pixley, Synopsys

"High-level to RTL equivalence and model checking of high-level designs"

Dr. Pixley will speak on topics related to high-level to RTL equivalence and model checking of high-level designs. He will also talk about the general issue of equivalence checking of hardware models.

Carl Pixley received a Ph.D. degrees in Mathematics from SUNY-Binghamton. He was on the faculties of U. Texas, Austin and Southwest Texas State U. Dr. Pixley also worked at Burroughs Inc. MCC, Mitsubishi Electric, nine years at Motorola and 4½ at Synopsys Inc. He has pioneered work in BDD-based Model Checking, Boolean Eqivalence, Alignability equivalence, Constraint-Based Verification and C-to-RTL verification. He has five patents and six patents pending. He is a member of the IEEE and the Mathematics Association of America, has served on the program committees of IEEE ICCD, ICCAD, CAV, DAC, DATE, FMCAD, HLDVT and Memocode and is verification editor for IEEE Design and Test. He (with Jun Yaun and Adnan Aziz) has recently published a Springer book on Constraint Based Verification.

"C-RTL Equivalence Checking: The bridge between ESL and RTL."

DRTL functional verification is one of the biggest challenges faced by IC design teams today. With more and more designers starting designs at the ESL level (for example architectural or verification models using C/C++ or SystemC) there is an increasing need to leverage these models for RTL verification. This session introduces a unique technology, sequential
equivalence checking (SEC), which enables formal verification of an RTL block against an ESL model. It substantially boosts coverage of the RTL and reduces the load on the simulation farms which are currently used as the primary method for RTL verification. This session will specifically address the value of a SEC based verification methodology, describe the unique points of this technology and recommend methodology guidelines for its effective deployment. The attendees will be able to perform early RTL verification by fully leveraging their investment in ESL models. This benefit would come without the need for testbenches, assertions or full chip simulations. SEC enables the users to find corner case bugs that can be missed by simulation, debug them more efficiently with short concise vectors and thus shorten the project time to achieve a golden RTL.

Before co-founding Calypto, Gagan was the Director of Engineering at Innologic Systems, a start-up in the formal verification arena. At Innologic, Gagan successfully managed the development of the company’s multi-million dollar flagship product from initial concept to adoption by more than 30 customers. Prior to joining Innologic, Gagan was an early member of the Ambit Design Systems engineering team, where he made substantial contributions to the BuildGates synthesis product. Before Ambit, he was a consultant with the Formal Verification group of the MIPS division of SGI. Gagan received an M.S and PhD in Computer Science specializing in Formal Verification of Hardware designs from University of Illinois at Urbana Champaign. He has B.S in Computer Science from Indian Institute of Technology, India.

Dr. Stephen Pateras, Senior Director, Corporate Product Marketing- LogicVision Inc.

"Innovations in Yield Learning. "

Design for Manufacturing (DFM) is a critical element of SoC design planning. The DFM space is still rapidly evolving and although not everyone agrees on what solutions and technologies make the most sense, most agree on the ultimate goal: improving yields. LogicVision offers a complementary and pragmatic approach to this problem. An often overlooked fact about BIST is that it is not only great at finding defects for go-nogo testing, but it also provides a great way of extracting detailed failure and performance information throughout the die. Hidden within this data are pointers to factors limiting the design’s yield. LogicVision’s unique automated data mining and analysis capabilities are capable of automatically uncovering these yield-limiting factors. Depending on the nature of the problem, the reported information is then used directly by designers to modify the design, or by the fab to adjust the process, or both. This post silicon process is called Yield Learning and has been identified within the recently published ITRS roadmap as the highest priority item for dealing with decreasing yields.

Dr. Stephen Pateras, Senior Director, Corporate Product Marketing- LogicVision Inc. has over 15 years of extensive background in DFT, BIST and fault tolerance and holds many journal and conference publications in these areas. Dr. Pateras received his Ph.D. in Electrical Engineering from McGill University.

Dr.

"Chip Instrumentation Solutions for SoC Analysis. "

Analysis and debug of SoCs presents challenging verification problems that can be significantly improved by the rights analysis tools and IP. The SoC debug problem is bigger than debugging the embedded processors – a system level debug approach is required to support the complexities of current and future SoC designs. On-chip instrumentation (OCI) is rapidly becoming the method of choice for addressing SoC verification/debug and for developing and integrating System-on-Chip (SoC) application code. A key advantage of OCI is in allowing real time internal visibility and debug control of embedded processors, embedded buses, and other IP blocks that are deeply buried in the silicon and not externally visible to users.  This presentation presents the principles of OCI, as developed by First Silicon Solutions (FS2) in providing a combined hardware/IP/software debug solution that allows sophisticated debug and trace capabilities for both processor and (bus) infrastructure components in a digital SoC. The presentation will discuss MED (Multi-Core Embedded Debug) based solutions for coherently addressing the debug requirements of systems with multiple processor cores, embedded buses, and complex blocks of user IP. The presentation will also discuss related issues such as integration of EDA and embedded debug tools and tradeoffs of standards based on-chip debug solutions in integrating the right debug capabilities into an SoC design.

Dr. Neal Stollon is Director of Technical Marketing with First Silicon Solutions, a Division of MIPS Technologies. He has over 20 years digital design and processor development experience at Texas Instruments, LSI Logic, Alcatel, and others. Dr. Stollon has a Ph.D in EE, is a Professional Engineer, has written over 35 papers and has 7 patents awards or in process.

Dr.

"Future direction of virtual system prototyping."

Robert Bedichek, PhD, has 30 years of software, hardware, and architectural design experience. He was formerly an Advanced Micro Devices Fellow, Director of Software Products for Transmeta Corporation, a researcher in MIT's Computer Architecture Group, a computer architect at Intel Corporation, as well as doing extensive work in embedded systems and compilers.

  5:15 pm - 6:15 pm

Panel

Panel: EDA Challenges for Complex SoC and ASIC Designs

Moderator: Dave Bursky, Semiconductor Editor, EETimes Magazine
 

Dave Bursky, Editor-at-Large, EETimes

Moderator

Dave Bursky, Editor-at-Large for Electronic Design magazine, joined Electronic Design in 1973, and has worked in various editorial positions, amassing more than 30 years of experience covering technology and product developments in the electronics industry.  Promoted to Editor-in-Chief in the fall of 1999 and to Editor-at-Large in early 2003, he has been responsible for defining the direction and content of Electronic Design. In addition to the editorial management responsibility, he has covered all aspects of Digital Semiconductor Technology, from processes to architectural definition, and from testing to circuit applications, for the magazine. He travels extensively around the U.S. as well as to Asia and Europe to interview company executives, and to attend trade shows and symposiums.  Additionally, Dave is one of several Electronic Design editors awarded the Jesse H. Neal award for Editorial Excellence. In 1988 he was described by an article in the San Jose Mercury News newspaper as one of the 100 most influential people in Silicon Valley. He has also taught digital logic technology at the former RCA Institute in New York City, and has been a guest lecturer at the Naval Post-Graduate School in Monterey, Calif.. Additionally, he has served on the program committees of numerous IEEE and commercial conferences, and has also moderated and organized technical presentation sessions at IEEE and commercial conferences. He has also authored six books on topics ranging from personal computers to semiconductor memories.  Prior to joining Electronic Design in 1973, he worked as a civilian electronics engineer at Fort Monmouth, N.J. on tactical computer systems and secure communication systems. Dave holds both Bachelor's and Master's degrees in Electrical Engineering from the City College of the City University of New York (1971 and 1973, respectively).  Dave lives in Silicon Valley and is married and has two children. In his spare time, he enjoys reading, stamp collecting, electronics (home-brew computing), and traveling.  

Jerry Frenkil, CTO, VP and General Manager, Silicon Business Unit
Sequence Design.

Panelist

Jerry Frenkil was one of the original founders of Sente, Inc., and has over 22 years of experience in the semiconductor and EDA industries. While at Sente, Mr. Frenkil was the Vice President of Low Power Design, where he led the services and applications activities. Prior to co-founding Sente, Mr. Frenkil was an independent consultant focused on IC design. He also held the position of Design Manager for VLSI Technology. Mr. Frenkil holds a BS in Electrical Engineering from the University of Texas. He has published papers on IC and Low Power Design, and holds several patents on circuit design and design automation.  

Max Lloyd, President and CEO, ViASIC.
 

Panelist

Max was previously vice president of business development at ASIC International (Ai) (Oak Ridge, Tenn.). While at Ai, Mr. Lloyd built the sales and marketing infrastructure, oversaw product direction, and grew revenues by more than 500% in less than two years. He was a key member of the management team that prepared the company for acquisition and then sold the company to Flextronics (Nasdaq: FLEX) in 2001. Before Ai, he was head of East Coast sales for Avant! Corporation with responsibility for over $50MM in sales, which was recently acquired by Synopsys Inc. (Nasdaq: SNPS). Other experience includes sales, product and engineering positions with the IT arm of American Express. Max received a degree in Mathematical Science and Computer Science from the University of North Carolina at Chapel Hill.  

Robert Jones,  Sr. Director, Custom Design Business Unit, Magma Design Automation
 

Panelist

Robert Jones is senior director of Magma’s Custom Design Business Unit. With over 22 years in the semiconductor and EDA industries, he drives the division’s product marketing and management. Coming to Magma via the Silicon Metrics acquisition, he held various business and technical roles at Synopsys, Avanti, and AMD.

AK Kalekos, CoWare, Vice President of Marketing and Business Development.

Panelist

AK Kalekos has more than twenty-five years of high tech business and marketing management experience. Prior to joining CoWare as Vice President of Marketing and Business Development, Kalekos was a general partner with Telos Ventures. Previously, as a senior vice president at Cadence Design Systems, he was a key contributor to the company's strategic re-direction and expansion of its business model from a tools provider to a tools and services provider. Kalekos developed his business creation skills by working in high-growth companies and start-ups such as Computervision Corp. in the 1970s, and Versatec and Mentor Graphics in the 1980s. He has held senior management positions in engineering, marketing, and divisional general management in the United States and Europe.
 

Dr. Adriaan Ligtenberg, President, CEO and co-founder of Takumi Technology.

Panelist

Dr. Ligtenberg is the President, CEO and co-founder of Takumi Technology Corporation located at the heart of Silicon Valley. Takumi Technology, founded in October 2003, delivers complete end-to-end GDSII to volume manufacturing solutions.
The company provides unique know-how and methodologies for substantial improvements in mask turnaround time and printability. Takumi Technology is currently engaged or has delivered solutions at 90nm, 65nm, and 45nm nodes. Since June 2002, Dr. Ligtenberg engaged in a special Cadence assignment as the Chairman and CEO of SpinCircuit. SpinCircuit was spun out of Cadence in 2000 to provide enterprise software solutions for product life management. Its strategic partners include Flextronics and Avnet. The company was acquired by Cadence in November 2002. Dr. Ligtenberg joined Cadence Design Systems, Inc. in September 1999 as Senior Vice President, Worldwide Services, responsible for approximately $350M in revenue.  In December of the same year, the group also included the worldwide customer support, Cadence Interactive and Design Environment units, and became known as the iDesign Environment Group. Since July 2000, Dr. Ligtenberg has led Cadence's eMerging Business unit, chartered to develop and grow new business areas for the company.   Dr. Ligtenberg sits on the board of several companies and is an active investor. Prior to joining Cadence, he was (1997–1999) CEO of A3 Ventures, a strategic consulting and investment company. He was the founder (1990–1997) of Storm Technology Inc., a digital imaging company instrumental in making JPEG the international standard for the storage and exchange of still images. He was also a co-founder (1989–1990) of C-Cube Microsystems, Inc., a company that became a leading provider of integrated circuits and created international standards for the compression of digital images and full motion video. Prior to his activities at C-Cube, Dr. Ligtenberg led the Image Systems Group at AT&T Bell Laboratories (1984–1989). He also held the position of associate professor of Electrical Engineering at Princeton, and was the recipient of the Computer Architecture Chair at the University of Amsterdam from 1989–1991. Dr. Ligtenberg earned his Ph.D. in Computer Science from the Swiss Federal Institute of Lausanne, and his M.S. in Engineering from the Delft University of Technology in the Netherlands.

5:15 pm - 6:15 pm

Panel: EDA Challenges for Complex SoC and ASIC Designs

Moderator: Dave Bursky, Semiconductor Editor, EETimes Magazine

Panelists:

1. Jerry Frenkil, CTO, VP and General Manager, Silicon Business Unit Sequence Design.

2. Max Lloyd, President and CEO, ViASIC

3. Robert Jones, Sr. Director, Custom Design Business Unit, Magma Design Automation

4. Dr. Heinrich Meyr, RWTH Aachen University and Chief Scientific Officer CoWare.

5. Dr. Adriaan Ligtenberg, President, CEO and co-founder of Takumi Technology.