Savant Company Inc

8:45 am - 12:00 am	CPUs & DSPs for SoC Applications
9:45 am - 10:00 am	Coffee Break

	TBD
12:00 pm - 1:00 pm	Lunch
1:30 pm - 4:15 pm	Memory Sub-System for System-on-Chip Designs
	Dr. Leung, Wing-Yu is Executive Vice President, Engineering and Chief Technical Officer, MoSys Corporation "I need more memory: Do I trench or do I stack?" Being able to embed large amounts of memory into System on Chip devices has long become a key requirement. 1T-SRAM® technologies have delivered optimal combinations of high density, low power, and high-speed memory products across multiple process generations. As the semiconductor industry keeps its quick path to atomic dimensions, high-density memory designers face the challenge of dealing with shrinking semiconductor structures and still store data reliably. From a physical perspective, there are two leading strategies for creating very dense memory bit cells - namely trench and stacked capacitor implementations. This paper will compare these two alternatives on qualitative and quantitative ways. Aspects like resulting silicon area; energy consumption; performance; manufacturability; reliability, and scalability to smaller geometries will be analyzed. Leung, Wing-Yu is Executive Vice President, Engineering and Chief Technical Officer and a board member. Prior to joining the company, Dr. Leung served as a technology consultant to several high technology companies. Prior to that time, Dr. Leung served as a member of the technical staff of Rambus, and as a senior engineering manager at Integrated Device Technology, Inc. where he managed and participated in circuit design activities. Dr. Leung earned his bachelor's degree in Electrical Engineering from the University of Maryland, a master's degree in Electrical Engineering from the University of Illinois and a Ph.D. in Electrical Engineering and Computer Science from the University of California at Berkeley.
	Michael Fliesler, Vice President of Engineering Kilopass Technology, Inc. "An embedded non-volatile memory, using standard logic CMOS, for SoC Design" System-on-Chip (SoC) platforms require non-volatile memory for firmware code storage, configuration, encryption, or trimming of analog blocks. Previous technology used either mask-programmed ROM (not field-programmable), a separate Flash memory chip, or embedded Flash technology, which adds cost, and can compromise IP security. This paper describes a novel high-density, non-volatile memory implemented in standard logic CMOS process. No additional mask or processing steps are required. The memory is available at several technology nodes (0.18u, 0.15u, 0.13u, 90nm) at multiple foundries. The hard macro IP blocks feature simple program and read operation. The presentation will cover the benefits, target applications and the basic design methodology to use this new memory IP technology for low ( 8 bits) to high density (up to 256Mb)embedded applications. The technology will be described and compared to other programmable technologies. Examples of cost and time-to-market reduction will be presented, plus applications to SoCs requiring embedded code storage for firmware, identification or security applications. Mr. Fliesler has over 30 years of experience in the semiconductor industry, with 20 years specialized in the field of FLASH, EPROM, and EEPROM development. Mr. Fliesler was formerly Director of Design in the Flat Panel Display Division at National Semiconductor. Prior to National, he was Director of Engineering Services at AMD in the Flash Memory Group. Mr. Fliesler holds six patents and has published five technical papers. He received the BS and MS degrees in Electrical Engineering from Stanford University.
	Dr. You-Pang Wei, President & CEO, Legend Design Technology "Memory IP Characterization and Simulation for Yields and Reliability" Presentation Abstract: SoC design, once logic dominant, has become memory dominant. With an emphasis on yields and reliability, we'll present a comprehensive solution for memory IP characterization and simulation by using CharFlo-Memory!, MSIM and Turbo-MSIM. Instead of interploating or extrapolating in conventional memory compiler model, CharFlo-Memory! generates timing and power models on a 'per-instance' basis that reflect the reality of silicon. To ensure silicon yields of SoC designs, CharFlo-Memory! can prevent reliability problems (e.g. glitch, metastability and noise margin etc.) in determiningg the true setup and hold time, and clock cycle. This solution has been successfully used on 90nm and 65nm memory compilers with silicon proven. CharFlo-Memory! has been adopted by major foundries, IDMs and fabless design companies. Dr. You-Pang Wei is President & CEO of Legend Design Technology, Inc. Dr. Wei has over 20 years R & D and management experiences in memory circuit designs and simulations, timing analysis and layout at AMD, Intel, Meta-Software, Performance CAD, and Mentor Graphics. He was the HSPICE chief architect and manager at Meta-Software. Dr. Wei received a B.S. degree in electrical engineering from National Taiwan University, and a M.S. degree and Ph.D. degree in electrical engineering from University of Illinois at Urbana-Champaign.
3:00 pm - 3:15 pm	Coffee Break
4:15 pm - 5:30 pm	Panel: Memory Sub-System for System-on-Chip Designs
Panelist Names	Panel: Memory Sub-System for System-on-Chip Designs Moderator: Dave Bursky, Editor-at-Large, Electronic Design Magazine . Panelists: 1. Robert Payne, Senior vice president and general manager of System Technology and Architecture, Philips Semiconductor 2. R. Mark Gogolewski, CTO, Denali Software 3. Phillip LoPresti, Associate Vice President and General Manager, Custom LSI Solutions, NEC Electronics America, Inc. 4. Jauher Zaidi, CEO of Palmchip. 5. Yohji Watanabe, Embedded Memory Design Dept. SoC R&D Center, Toshiba Corp. 6. Jon Kang, Senior Vice President of Technical Marketing, Samsung Semiconductor
4:30 pm - 8:30 pm	Conference Exhibit & Reception Open

3rd International System-on-Chip (SoC) Conference & exhibit

Detailed Program Information for wednesday, November 2, 2005*

8:45 am - 12:00 am	New Trends and Approaches for ASIC & SoC Designs
9:45 am - 10:00 am	Coffee Break
	Dr. Kevin M. Monahan, Vice President of Technology, Parametric Solutions Group KLA-Tencor Corporation "Conjoint APC and DFM Strategies for SoC Yield at 65nm and Beyond" Most semiconductor manufacturers expect 193nm lithography to remain the dominant patterning technology through the 32nm technology node. Even now, the interaction of more complex SoC designs with shrinking process windows is having an impact on pattern limited yield. Ramp delays of several months are common, leading to revenue losses in the tens of millions of dollars per product and reduction of ROI for 300mm factories. Ramp delays occur primarily for two reasons: lengthy process optimization for smaller yield windows and increased time allocated for more complex intra-field corrections. The semiconductor industry is attacking this problem using design for manufacturability (DFM) and advanced process control (APC) strategies. The primary goal of DFM is to enlarge the process yield window; and the primary goal of APC is to keep the process in that yield window. In this work, we show that feedback of super-accurate process metics will be a critical component of conjoint DFM and APC strategies at the 65nm node and beyond.
12:00 pm - 1:00 pm	Lunch
1:30 pm - 4:15 pm	EDA Tools & Methodologies for 65nm and Beyond

3:00 pm - 3:15 pm	Coffee Break
	Dr Filip Thoen, CTO, Virtio "Efficient Debugging of Heterogeneous SoCs and peripherals" Simulation models of multi-core SoC platforms enable advanced debugging capabilities of wireless devices. One of the most advantageous is the ability to stop all SoC processors at once, or only a single process while executing another. Debugging heterogeneous multi-core SoC’s is usually difficult using JTAG and physical hardware because JTAG scan chains only stop one processor at time. This makes it nearly impossible for the software developer to understand the exact system state while the other processors continue running. In this session you will learn how to easily debug a multi-core platform with simulations and existing software debuggers. Instruction set simulators and even JTAG/boundary scan tools working with the silicon can not stop individual processors or processes. This capability will become increasingly critical as most future SoC/ASSP wireless devices will have multiple cores and will be highly integrated. Learn a better way to debug your complex wireless SoC devices using simulated platforms along with your current software debugger. Filip Thoen has over 15 years experience in high-level synthesis, retargetable code generation, HW/SW co-design and system-on-chip (SoC) design. Prior to joining Virtio, Filip worked as research staff engineer and chief system architect at National Semiconductor. Filip received his Ph.D. in electrical engineering from the Catholic University of Leuven (Belgium) and worked as a researcher in the IMEC research institute.
4:15 pm - 5:30 pm	Panel: Myth or Reality: Power Reduction at All Levels of Design Abstraction Design for low power is a thread that binds together all levels of chip-design abstraction, from the system level down to layout and silicon processing. Power reduction techniques at the system level are necessarily tied to power reduction techniques at the layout level and levels in between. Similarly, power reduction at the layout level has system-level implications. Consequently, significant opportunities for saving power exist at all levels of abstraction and are interrelated in such a way that design for low power must concurrently consider all levels of abstraction. The panelists will each talk about design techniques and best practices for reducing power.
	Richard Gordon, Independent Consultant Moderator Richard Gordon is an entrepreneur and independent consultant specializing in electronic design automation (EDA) software, low-power system-on-chip design, and quantum information science and technology (QIST). He hosts the MIT-Stanford-Berkeley Nanotechnology Forum on QIST. Most recently, he co-founded Tera Systems, an EDA startup whose chip design products are used by IBM, LSI Logic, and NEC. Prior to Tera Systems, he helped start Silicon Compiler Systems (SCS), which developed microprocessor (MPU) and DSP design software used by Intel, TI, and Sun Microsystems; SCS was sold to Mentor Graphics in 1990. He was a Member of Technical Staff at AT&T Bell Laboratories from 1979 to 1985 in the High-End MPU Design Division responsible for creating the world’s first 32-bit CISC and RISC processors. Mr. Gordon has an MSEE from Stanford University and a BSEE from Brown University.
	Michael Burstein, CTO, Founder, Golden Gate Panelist The Golden Gate product development team is led by Dr. Michael Burstein, EDA industry veteran, most recently Vice President of Physical Design at Synopsys, Inc. He was co-founder of two successful EDA startups, Gambit Automated Design, Inc. (1991-1999), acquired by Synopsys, Inc., and Descartes Automation Systems (1986-1989), acquired by Mentor Graphics. Dr. Burstein also held engineering positions at Fairchild and IBM.
Panelist Names 4:15 pm - 5:30 pm	Panel: Myth or Reality: Power Reduction at All Levels of Design Abstraction Moderator: Richard Gordon, Independent Consultant Panelists: 1. Dhrumil Gandhi, VP Engineering, ARM. 2. Steve Leibson, Technology Evangelist, Tensilica 2. Wing-Yu Leung, CTO, MoSys. 3. Susan Runowicz-Smith. Cadence--Silicon Design Chain Initiative. 5. Michael Burstein, CTO, Golden Gate Technology. 6. TBD