Call for Sponsors & Speakers

The 10^th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

October 24 & 25, 2012 - Hilton Irvine, California

9th International SoC Conference In Pictures. . .

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Detailed Program Information for Wednesday, November 3, 2004*

8:00 - 8:15

Farhad Mafie, President and CEO of Savant Company Inc.

Farhad Mafie has over 20 years of experience in electronic and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer solutions based on ASSP and SoC Models.

Farhad has also worked at Lucent Technologies, Toshiba Information Systems, Unisys, and MSI Data in strategic marketing and project engineering capacities.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.

His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies.  

Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

  8:15 pm -  8:45 am

Jordan Selburn, Principal Analyst, Core Silicon, iSuppli Corp

Jordan came to iSuppli with decades of extensive experience in ASIC, programmable logic and semiconductor intellectual property (IP) analysis, product marketing, and engineering development. Prior to joining iSuppli, Jordan served as the Director of Product Marketing for Amphion Semiconductor, where he was tasked with managing the technical product marketing team. He launched products in all of Amphion’s product families in addition to providing in-depth sales support for the products and the IP business model. Prior to his tenure with Amphion, Jordan was the Principal Analyst for ASIC and IP at Gartner Group/Dataquest and as such was responsible for the evaluation and analysis of semiconductor IP as well as the ASIC and programmable logic markets. He formulated and presented tracking and forecasting on technology and market trends with particular emphasis on system-level integration as part of his duties at Gartner Group/Dataquest.  Marketing Manager and Product Line Manager positions at LSI Logic preceded his employment at Gartner Group/Dataquest. At LSI Logic, Jordan was charged with establishing product positioning and pricing for their production ASIC products. In addition, he generated technical requirements and provided marketing direction to product development teams along with creating business plans for 0.6 micron and 0.35 micron technologies. Before LSI Logic, Jordan was an ASIC Technology Manager and a Corporate Applications Engineer at Valid Logic Systems/Cadence Design Systems and was also associated with Agilent/EEsof, Inc., and Harris Corporation in various engineering capacities. Jordan holds a Master of Science in Engineering Economic Systems from Stanford University in addition to an MBA with distinction from Santa Clara University and a BSEE with honors from the University of Michigan.

  8:45 am -  9:15 am

Keynote

Dr. Giovanni De Micheli, Stanford University

Keynote

Giovanni De Micheli is Professor of Electrical Engineering, and by courtesy, of Computer Science at Stanford University. Previously he held positions at the IBM T.J. Watson Research Center, Yorktown Heights, New York, at the Department of Electronics of the Politecnico di Milano, Italy and at Harris Semiconductor, Melbourne, Florida. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979) and an M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

His research interests include several aspects of design technologies for integrated circuits and systems, with particular emphasis on synthesis, system-level design, hardware/software co-design and low-power design. He is author of Synthesis and Optimization of Digital Circuits (McGraw-Hill, 1994), co-author or co-editor of five other books and of over 270 technical articles. He is, or has been, member of the technical advisory board of several companies, including Magma Design Automation, Coware, Aplus Design Technologies, Ambit Design Systems and STMicroelectronics.

Dr. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He is a Fellow of ACM and IEEE. He received the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000. He received the 1987 D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS and two Best Paper Awards at the Design Automation Conference, in 1983 and in 1993.  He is Past President of the IEEE CAS Society. He was Editor in Chief of the IEEE Transactions on CAD/ICAS in 1987-2001. Dr. De Micheli was the Program Chair and General Chair of the Design Automation Conference (DAC) in 1996-1997 and 2000, respectively. He was the Program and General Chair of the International Conference on Computer Design (ICCD) in 1988 and 1989, respectively. He was also co-director of the NATO Advanced Study Institutes on Hardware/Software Co-design, held in Tremezzo, Italy, 1995, and on Logic Synthesis and Silicon Compilation, held in L'Aquila, Italy, 1986. He is a founding member of the ALaRI Institute at Universita' della Svizzera Italiana (USI), in Lugano, Switzerland, where he is currently a scientific counselor.

  9:15 am -  9:45 am

Keynote

Dr. Ivo Bolsens, Chief Technology Officer, Xilinx, Inc.  

Keynote

Ivo Bolsens joined Xilinx in June 2001 as vice president and chief technology officer (CTO). He is responsible for identifying Xilinx technologies and talent as well as heading up the Xilinx Research Laboratories, which focus on advanced research in the area of programmable logic. Mr. Bolsens came to Xilinx from the Belgium-based research center IMEC, where he was vice president of information and communication systems. He began there in 1984, holding various positions of increasing responsibility. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high level synthesis of DSP hardware, HW/SW co-design and system-on-chip design.  Bolsens earned his master's degree in electrical engineering and his Ph.D. in applied science from the Catholic University of Leuven in Belgium. He is author and co-author of more than 100 papers in the field of VLSI design, CAD, embedded system design, and wireless communication. He is also co-author of the book, "High Level Synthesis for Real Time Digital Signal Processing."

New Trends and Approaches in ASIC and SoC Design

Track Chairman: John Miklosz

Editor-in-Chief/Publisher of SOCcentral.com

John Miklosz,

Track Chairman

He began his electronics publishing career with Electronic Engineering Times in 1980 and joined Computer Design magazine in 1984, where he rose from executive editor to editor-in-chief and publisher, and was the founding publisher of Portable Design magazine. Prior to starting SOCcentral in the spring of 2003, he was Editorial Director for TechOnLine.

Jauher Zaidi, CEO of Palmchip Corporation and Member, Savant Board of Advisors

"Benefits of Custom ASSP vs ASIC"

Jauher Zaidi is Chairman & CEO of Palmchip Corporation.  Jauher has over twenty years of experience in system design and integration. Before founding Palmchip in 1996, he was involved in system-on-chip (SoC) integration at Quantum Corporation. Jauher received his BSEE and MSEE degrees from Pacific States University in Los Angeles, California. He has also participated in many SoC panels and is a recognized expert in the area of SoC development. 

Alain Bismuth,  Vice President, HardCopy Product Group,  Altera Corporation

"SoC Design Using Programmable ICs & Structured ASICs "

The structured ASIC category has emerged to minimize the cost, development time, and risk associated with ASIC development. The optimum structured ASIC approach requires a design methodology that provides an FPGA prototype that can be seamlessly migrated to the structured ASIC as well as facilitate in-system verification. Of the various structured ASIC offerings currently available, only those based on programmable logic can truly deliver on these requirements. My presentation will detail both the business and the technology challenges that drive the need for having design options at your fingertips and the benefits of using an FPGA-based, structured ASIC design methodology.

Alain Bismuth joined Altera in January 2001 as the Vice President of New Market Development. He is currently Vice President of the HardCopy Product Group, in charge of developing and managing Altera’s structured ASIC business worldwide.  Bismuth has more than 20 years of business experience in the semiconductor industry.  Prior to joining Altera, Bismuth was Vice President of DVD Player Products at Oak Technology, where he led the group that introduced the world’s most integrated complete chipset solution for DVD player products.  Bismuth has also held marketing management, sales, and engineering positions at LSI Logic and IBM Semiconductor.  He holds a Master of Science in Solid State Physics from Ecole Centrale de Lyon in France.

Patrick Dorsey,  Product Line Director,  EasyPath FPGAs and Configuration Products.  Xilinx, Inc.

"FPGAs vs. Structured ASICs:  Low-Cost, Volume Solution for SoC Design"

With the introduction of the platform FPGA, customers are benefiting
from system-on-chip capabilities previously not available in a programmable solution. More than ever before, the market is now demanding not only lower cost but also greater flexibility to reduce the cost and risk of ASIC development. An innovative approach is necessary to maximize flexibility while reducing cost. This presentation will examine breakthrough FPGA technology that for the first time provides unique programmable flexibility at an overall cost below Structured ASICs.

Patrick Dorsey is the Product Line Director for the development and marketing of EasyPath FPGAs and Configuration Products at Xilinx Inc.   Patrick has been involved in technology marketing and solutions development for over 17 years.  Previous to his current position, he drove the product development and marketing strategy in the mid 1990’s for both the Xilinx XC5200 and Spartan product lines as Product Manager.  Patrick was also Director of Marketing for Collaboration and Communication systems development at Sun Microsystems and has worked in marketing, consulting and sales roles at Intel Corporation, Texas instruments, and Deloitte Consulting.  Patrick holds a B.S. in Computer Engineering and a Masters in Business Administration from the University of Michigan.

John Gallagher, Senior Director ASIC Synthesis Marketing, Synplicity, Inc.

"Structured/Platform ASICs:  Are They Painkillers or Vitamins for the Electronics Industry?"

With the emergence of Structured and Platform ASIC architectures over the past couple of years, there has been an underlying question:  Are these architectures a short-term solution for immediate problems (i.e., painkillers), or are they an evolutionary step toward better and more efficient system design (i.e., vitamins)?  This presentation will look at factors such as design-for-manufacturability (DFM), signal and power integrity management in complex SoCs, manufacturing process advantages for the silicon vendor, and design flow productivity to determine the longer-term roadmap for Structured/Platform ASICs.  In addition, this paper will discuss differences in access to advanced process technologies between cell-based and Structured/Platform ASIC architectures for SoC designs.

John Gallagher holds a B.S. in Engineering and an M.B.A. from Cornell University. He is the Senior Director for Synplicity’s ASIC synthesis technologies. Prior to joining Synplicity in 1999, he served as director of place and route marketing at Cadence Design Systems. He has also held ASIC marketing positions at LSI Logic and Hewlett Packard.

  1:00 pm - 1:30 pm

Keynote

EDA Tools and Methodologies for 90nm and Beyond

[Sponsored by Atrenta Corporation]

Steve Carlson, Director, Cadence Synthesis Team

"Front-End Design for Nanometer SoCs" 

Power ... it used to seem that everybody wanted it. Now, everybody is trying to get rid of it. Power is reaching near-crisis proportions in the chip design world. Recently, Gerald Marcyk, Director of Components Research at Intel Labs, was quoted as saying, "Smaller and faster just isn't good enough anymore. Power and heat are the biggest issues for this decade." Power is not just an issue for wireless designers. Tethered products are also facing the power predicament head-on. In booming product areas like the wired world of networking, power per square foot is a key issue.  For wireless applications, battery life and reliability are two of the chief concerns regarding excess power usage. In a Darwinian sort of way, those "portable" devices that constantly need to be plugged in for recharging are destined to extinction. Managing power is a matter of survival. Yet another perspective came from a 2000 environmental conference in Europe where it was reported that the energy needed to transport 2Mb of data through the Internet is equal to 1 pound of coal. Remember that next time you are web surfing.  Power gluttony has a number of undesirable effects. Chip package costs get significantly higher as power consumption increases. The cost of a package for a chip that dissipates 50W or more far exceeds the cost of fabricating the chip itself. Excessive switching current leads to product reliability issues via metal migration and thermal stress processes. System cooling costs are starting to be a primary consideration. The system power density (watts per square foot) is now a real facilities management nightmare, as adequate power and cooling need to be provided to power-dense locations such as server farms and ISP sites.  From the silicon process technology up to systems architecture, there are significant advancements being made that give us cause for hope for an end to the power crisis. However, as progress in process technology marches forward, new challenges are always mounting. This paper focuses on some of these key new challenges and the accompanying design automation technologies that might alleviate them.

Steve is a Director on the Cadence Synthesis team.  In that role he is focused on marketing the solution for the best Quality-of-Silicon (chip speed, area, power, test measured after wires).  Carlson reports to Chi-Ping Hsu, Corporate VP for New Synthesis at Cadence.  Steve joined Cadence in April in 2003 via the Get2Chip acquisition, where he was the VP of Marketing.  Prior to Get2Chip, Steve was the CEO of Tharas Systems, a hardware acceleration company.  Steve has also held various management positions at Escalade, LSI Logic, United Technologies and Synopsys.  At Synopsys, Steve was a part of the original Design Compiler technical team responsible for timing analysis and optimization.  Steve was the author of the industry’s first book on high-level design: Introduction to HDL-based Design Using VHDL.  Steve has a BSEE, a BSCS, and an MSEE, all from the University of Colorado.

EDA Tools and Methodologies for 90nm and Beyond Cont.

Steve Roddy, Director of Product Marketing, Tensilica

"Instantly Create SoC Hardware Blocks from C Algorithm Descriptions"

With 90nm, 65nm, etc., geometries, the need for an effective system behavior modeling increases to manage the design complexity. The C programming language is the natural language of choice for algorithm developers and systems architects to capture and model system behavior. For more than a decade, the SoC design industry has struggled to find a path that takes those C specifications of algorithms and automatically or systematically transforms them into efficient chip designs. A variety of approaches - with buzzwords like behavioral synthesis, C language hardware synthesis, and ESL - have fallen short because they all have tried to conquer a nearly intractable problem - transforming a language designed to be executed in a sequential manner on a microprocessor into a highly parallel system of interoperating, non-programmable hardware elements. Simply transforming the C code no longer works effectively for complex system designs. A new and different compiler design and approach is needed to be effectively used/applied on a highly parallel architecture of today’s high-performance microprocessors. We have developed an advanced compiler that automatically tailors the Xtensa LX microprocessor into a highly efficient machine that executes the original C code faster. The tailoring process takes literally minutes. Using the XPRES Compiler, designers often find that the automatically generated Xtensa LX processor is fast enough to meet their system’s specifications. In other cases, engineers can further extend the processor to get even higher performance.  This presentation will provide an overview of key challenges with current C compilers for complex designs, provides a design approach based on a new and advanced compiler, and will provide performance results for a number of benchmarks as well as other application tasks common to many SoCs being designed today.

Steve Roddy has been Director of Product Marketing for Tensilica since 2000.  His career spans 20 years as an engineer and marketing professional in the semiconductor, EDA and computer industries. Prior to joining Tensilica he was Vice President of worldwide sales and marketing for Amphion, an audio and video IP licensing company, and held previous marketing roles at Cadence, Synopsys and LSI Logic. His engineering experience included computer system and processor design roles for Burroughs and Gould.  He holds a Bachelor's degree in Electrical Engineering from UC Berkeley and an MBA from the Anderson School of Management at UCLA.

Dr. Tamara Papalias, Department of Electrical Engineering, San Jose State University

"Trends in SoC Testing & Verifications" 

This presentation is an overview of current trends in testing and an explanation of the upcoming challenges facing SoC products.  The combined effects of process scaling and increased system integration are forcing the industry to reexamine testing methods.  Now, system designs push the limits not only of a process but also of the test equipment.  With the increased popularity of SoCs, testing cycles grow longer and product testing becomes more expensive.  To minimize cost, some of the testing will need to be moved from the tester into the silicon.  These integrated test circuits can enhance process control, ease test program development, and allow access to internal nodes of complicated systems.  While digital circuits enjoy clearly defined methodology for lowering test costs by integrating test structures, analog and mixed-signal products lack standard design for test (DfT) or built-in self-test (BIST) structures.  Inclusion in analog and mixed-signal systems is especially critical as shrinking process variations force more tests to be performed at-speed.  These design speeds are approaching wire limitations that stress both the package and the tester setup, eventually forcing the inclusion of test structures in all SoCs.

Dr. Tamara A. Papalias received the B.S., M.S., and PhD. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1995, 1995, and 2003, respectively. She is Professor of Electrical Engineering at San Jose State University, San Jose, CA.  She held a summer staff position at Acuson in 1992 and at Elantec Semiconductor (now Intersil) from 1993 through 2001. Her research interests include engineering education, analog and RF CMOS circuit design, and DfT (design for test) systems.  She is currently collaborating with local companies to develop a set of courses on test engineering, from debugging to tester operation.

  4:30 pm - 5:45 pm

Panel: EDA Tools and Methodologies for 90nm and Beyond

Michael Santarini, Senior EDA Editor at EE Times

Moderator

Michael Santarini is the Senior EDA Editor at EE Times. He has covered EDA and IP for EE Times for seven years. At EE Times, Santarini has distinguished himself as an investigative journalist, having won a CMP Media award for "best exclusive story" last year for an article covering a failed takeover of MIPS by licensees. He is a candidate for another "best exclusive story" this year for a two-part expose on Cadence Design Systems. In his seven years of service, Santarini has broken over a dozen M&A stories, including the Synopsys acquisition of Everest Design and Cadence's acquisitions of SPC and Plato.  Before joining EE Times, he was an Associate Editor at now-defunct Integrated System Design Magazine for two years.  Santarini has a BA in English from Santa Clara University.

Rich Goldman, Vice President of Strategic Market Development, Synopsys, Inc.

Panelist

Rich Goldman is the Vice President of Strategic Market Development at Synopsys, Inc. In this capacity, he is responsible for guiding key partnerships for the company to provide a complete solution to its customers. Mr. Goldman joined Synopsys in August 1992 as an ASIC Core program manager. Before assuming his present position, he was an engineering manager and director of the semiconductor vendor program (SVP).

Before joining Synopsys, Mr. Goldman worked at Texas Instruments, where, as a manager in Engineering Workstation Support, he was responsible for electronic design automation libraries and design support software. Prior to TI, he was a software developer at IBM. Mr. Goldman is Chairman of the EDAC Interoperability Committee and has served on the EDAC board of directors. He also served on the board of directors of Atomic Tuna, an internet registry, from 1999-2000 and is chairman of the board of the Synopsys Outreach Foundation. Mr. Goldman holds a BSCS from Syracuse University, an MBA from the University of Dallas and an MS in Engineering Management, also from the University of Dallas.

Dr. Bernard Murphy PhD, Chief Technology Officer, Atrenta

Panelist

Dr. Murphy has nearly 20 years experience in design, sales, marketing and business development. He previously held senior positions with Cadence Design Systems, National Semiconductor and Fairchild. Dr. Murphy received both a Bachelor of Arts and D.Phil. in Physics from Oxford University.

Panel:  EDA Tools and Methodologies for 90nm and Beyond

Moderator:  Michael Santarini, Senior EDA Editor at EE Times.

Panelists:

1. Rich Goldman, Vice President of Strategic Market Development, Synopsys, Inc.

2. Robert Hum, Vice President & General Manager of Design Verification and Test, Mentor Graphics

3. Steve Carlson, Director Synthesis Team, Cadence Design Systems

4. Dennis George, Director, Product Marketing, Magma

5. Dr. Bernard Murphy, Chief Technology Officer, Atrenta

Detailed Program Information for Thursday, November 4, 2004*

  8:00 am - 8:15 am

  8:00 am - 8:15 am

Farhad Mafie, President and CEO of Savant Company Inc.

Farhad Mafie has over 20 years of experience in electronic and computer businesses and more than 10 years of university-level teaching experience.  Farhad is the former Vice President of Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).  He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer solutions based on ASSP and SoC Models.

Farhad has also worked at Lucent Technologies, Toshiba Information Systems, Unisys, and MSI Data in strategic marketing and project engineering capacities.  He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.

His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies.  

Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.

  8:15 am - 8:45 am

Keynote

Dr. Juan-Antonio Carballo, Venture Strategy Executive, IBM Corporation

Keynote: "IP Valuation Trends in the Context of Open Core Architectures"

Developing a System-on-Chip (SoC) has become a task that consumes enormous resources, including direct cost and overhead, and entails substantial quantifiable risk. The return on such an investment (ROI) must be unequivocally positive for the project to be undertaken. In this context, two market structure characteristics are needed. First, a healthy economic system for value-added Intellectual Property (IP) components, which in turn requires systematic yet practical methods for Intellectual Property (IP) valuation in SoC. Second, open industry standard organizations that provide (a) an organizational structure for developing an increasingly valuable ecosystem that rewards the key contributors, and (b) a standard plug-and-play infrastructure and methods that enable innovators to focus on creative additions – including large innovators as well as nimble venture-backed startups. We describe and model these components of the SoC ecosystem structure, and we apply them to estimate their increased benefit in the context of open core architectures.

Juan-Antonio Carballo is a Venture Strategy Executive at IBM Corporation, responsible for creating and managing strategic projects with top-tier Venture Capital firms and their portfolio companies. Prior to this role, Juan-Antonio was leading research in adaptive communications chips at IBM Research. He won an IBM Research Division award for his work in this area.  He filed near 20 patents and has over 15 publications in low-power design, communications systems, design economics, and electronic design management.  He is the Chair of the International Technology Roadmap for Semiconductors (ITRS) Design Chapter, and a member of the board and chairperson of the VSI Alliance (VSIA) R&D Pillar.  He has been on the committee of six symposiums and conferences, and was the General Chair for Electronic Design Processes 2004 in Monterey, CA. His prior work experience includes stays at Digital Equipment (currently HP) and LSI Logic. Juan-Antonio holds a Ph.D. in Electrical Engineering from the University of Michigan, an M.B.A. from the College des Ingenieurs (Paris), and a M.Sc. in Telecommunications Engineering from the Universidad Politecnica de Madrid.

  8:45 am -   10:45 am

Revitalizing the IP Model for SoC/ASIC Design

[Sponsored by Toshiba America Electronic Components, Inc.]

Ronnie V. Vasishta,  Vice President of Technology Marketing, LSI Logic Corporation

"IP - Art or Science?"

Ronnie Vasishta is Vice President of Technology Marketing and CoreWare® Engineering for LSI Logic Corporation.  He oversees the companywide strategic technology direction and the definition and development of LSI Logic’s technology products, including silicon technologies, intellectual property cores, design tools and methodologies, advanced packaging, embedded memory, and I/Os.  In addition, he has responsibility for direct marketing support for customers, sales, vertical market groups, and design centers.  Vasishta’s responsibilities also include the marketing and engineering of LSI Logic’s CoreWare® Engineering program, which includes CoreWare® methodology, development, and field support engineering, as well as interfaces with third-party IP providers.   

Steve Williams provides business development support to the ASIC & Foundry Business Unit at TAEC. He has been involved in many IP transactions as an IP user at TAEC and as an IP seller at 3DSP, LSI Logic and ARM. He received BS and MS degrees in Computer Engineering from Cornell University and has been further educated on-the-job in his 24 years in the semiconductor industry.

Business drivers, such as improved time-to-market and better resource utilization, are factoring ever more into the system-on-chip (SoC) development process. One widely accepted method to meet these goals is design reuse. Reuse of blocks from previous-generation chips or related chips within the same organization has long been an accepted reality. Additionally, acquisition of intellectual property (IP) blocks from internal or external sources is becoming more common among SoC design teams. However, the successful integration of these blocks to produce a working SoC depends upon many factors.  The VSIA Quality IP (QIP) metric addresses the general factors affecting IP reuse, as well as the factors specific to a particular type of IP.  We describe the structure of the QIP metric and its application to IP developers and IP integrators.

Kathy Werner is the co-chair of the VSIA IP Quality Pillar and is a Reuse Manager at Freescale Semiconductor, Inc., responsible for IP coordination, standardization and quality.  Prior to this role, Kathy was a Reuse Consulting Manager for Mentor Graphics, working with global semiconductor companies to define and implement internal reuse programs.  Kathy has received numerous awards from both Freescale and Mentor Graphics, as well as client recognition for her work in this area.  Kathy is a track chair for the DesignCon05 Business Issues.  Her previous work experience includes Advanced Micro Devices, Zenith Data Systems, and Allied Signal Aerospace.

Dr. Naveed Sherwani, Co-Founder, President & CEO of Open-Silicon

"A Fabless ASIC Model Based on Aggregation"

ASIC customers are pretty demanding, yet their demands are easy to summarize. They want reliable chips (chips should work as per spec!), on a predictable schedule (no surprises), at a reasonable cost.  There are two existing ASIC models: the Traditional ASIC Model (fully integrated design, fab and package) and COT (customer-owned design, with independent fab/package). Traditional model vendors have done well as far as silicon success is concerned; however, they have not done so well in the predictability/visibility arena and have done very poorly in the cost arena. This is largely due to their expensive cost structure, which leads to NRE amortization. This has led to a general perception that ASICs are expensive. COT provides more control and visibility to customers; however, due to low tape-out volume, the reliability depends on the quality of the design teams. Cost is still high due to amortization of expensive teams, design tools and the entire associated overhead.  A new open model, which relies on an ASIC vendor’s ability to aggregate all aspects of the ASIC supply chain, is bringing unprecedented freedom to the traditionally inflexible chip supply chain. The open model allows customers to be involved in the supply chain choices that not only reduce costs, but dramatically improve the chances of right-first-time silicon. As ASICs become increasingly complex and expensive, an open model that allows complete choice for every step in the process of designing and manufacturing a custom ASIC becomes even more appealing.

Dr. Sherwani has over 19 years of experience in technical engineering and general management and currently serves as the President and CEO of Open-Silicon, which he founded to bring cost-effectiveness, predictability and reliability to the ASIC market. Prior to founding Open-Silicon, Dr. Sherwani was the founder and General Manager of Intel Microelectronics Services where he led efforts to promote the use of disciplined ASIC methodologies to improve design efficiency and time-to-market.  Naveed co-architected Athena, the Intel microprocessor design methodology and environment that has been used in various leading microprocessors. Prior to joining Intel, he worked as a consultant for various telecommunications and computer companies, focusing mainly on ASIC design flow and cell library design to improve time-to-market. He also served as a Professor at Western Michigan University, where his research concentrated on VLSI Physical Design Automation, combinatorics, and graph algorithms. Dr. Sherwani is the author of the main textbook on Physical Design, Algorithms for VLSI Physical Design Automation, which is widely used at major universities around the world. In addition, he has authored or co-authored 3 books and over 100 articles on various aspects of Physical Design Automation and ASICs. In last 15 years, he has been a frequent speaker at DAC, ICCAD, International Conference on VLSI and other major conferences around the world. Dr. Sherwani received his Ph.D. from the University of Nebraska-Lincoln.

  11:05 am - 12:00 am

Panel: Revitalizing the IP Model for SoC/ASIC Design

Dr. Jim Lipman, Contributing editor for TechOnLine and SOCCentral; VP of Business Development and Client Services at Cain Communications 

Moderator

Prior to his positions at Cain Communications, Jim was co-founder, President and Editor-in-Chief for SemiView Inc., a start-up providing consulting and information services on application-adaptable ICs (AAICs).  Before SemiView, he was an independent consultant for the electronics industry, focusing on EDA tools and SoC/ASIC technology and design methodology. Jim’s editorial experience includes three years at TechOnLine, most recently as Content Director, responsible for all editorial material on TechOnline’s site that provides training and technical information for electronics engineers. Before TechOnLine, Jim spent 4½ years as EDN Magazine's ASIC and EDA Technical Editor. 

Previously, Jim was at VLSI Technology in various training, marketing and public relations roles.  Before VLSI, Jim worked at Hewlett-Packard in IC development and chip-design training, and at Texas Instruments in radiation-effects analysis and digital-chip design. Jim received his BSEE and MSEE degrees from Carnegie-Mellon University in Pittsburgh and his Doctorate in Electrical Engineering from Southern Methodist University in Dallas.  He also has a Master of Business Administration degree from Golden Gate University in San Francisco.  Jim is involved with a number of highly regarded technical conferences and symposia.  He served for several years on the Steering/Organizing and Technical Program Committees of the Custom Integrated Circuits Conference (CICC), has served as past Technical, Conference, and General Chairs for CICC, is a Technical Advisor for Wescon and is a past member of Wescon’s board of directors.  Jim is a senior member of the IEEE.

Guri Stark, Vice President of Marketing, Solutions Group, Synopsys

Panelist

As Vice President of Marketing for Synopsys' Solutions Group (SG), Guri is responsible for driving Synopsys' strategy, positioning and value proposition, targeting market segments and Synopsys' IP and Design Services solution offerings.  Guri has more than 25 years of experience in marketing, sales channel management and software development. He comes to Synopsys from Syntricity, Inc., where he was a company officer and held the position of Vice President of Marketing and Professional Services. Guri was responsible for product strategy, product management, marketing communication, branding, public relations, business development, application engineering, customer support and professional services.  Previously he was Vice President of Marketing and held other engineering, marketing and sales channel management positions at Encad, Inc., Autodesk, Inc., Spectragraphics Corp., and Auto-trol Technology.  Guri has an MBA from the University of Colorado and has an MS in Computer Science and a BS in Mechanical Engineering from Technion Israel University of Technology.

Panel:  Revitalizing the IP Model for SoC/ASIC Design

Moderator:  Dr. Jim Lipman, Contributing editor for TechOnLine and SOCCentral; VP of Business Development and Client Services at Cain Communications

Panelists:

1. Ronnie V. Vasishta,  Vice President of Technology Marketing & CoreWare® Engineering, LSI Logic Corporation

2. Guri Stark, Vice President, Synopsys

3. Richard Tobias, Vice President of the ASIC and Foundry Business Unit, Toshiba America Electronic Components, Inc.

4. Dr. Juan-Antonio Carballo, IBM

5. Dr. Naveed Sherwani, Co-Founder, President & CEO, Open Silicon

6. Kathy Werner, Reuse Manager, Freescale

CPUs and DSPs for SoC Platform Design

Steve Leibson, Technology Evangelist, Tensilica, Inc.

"Breaking Processor Core I/O Bottlenecks with Ports and Queues"

Processor cores are used to implement many tasks on SoCs, and they might be used for many more if certain fundamental bottlenecks are broken. Those bottlenecks include raw computational throughput and I/O bandwidth into and out of the processor. Processor-core vendors have experimented with generalized ways of improving their processors’ computational bandwidth, such as superscalar and VLIW architectures, but these methods do not even come close to fully exploiting the capabilities of nanometer SoC silicon, and they are quite expensive, in terms of gates or real estate, relative to the benefit they provide. Further, all processors suffer from extreme I/O bandwidth limitations created by the universally employed microprocessor bus architectures.  Tensilica recently introduced a configurable processor core, the Xtensa LX, that literally sweeps away both the computational-throughput and I/O-bandwidth limitations of other microprocessor cores. The Xtensa LX processor’s FLIX (Flexible-Length Instruction eXtension) architectural technology allows SOC designers to add computational resources precisely where they’re needed by a specific task or application. The Xtensa LX’s designer-definable Ports and Queues constructs allow SoC designers to add up to 1024 additional ports directly into the processor’s execution units, boosting the processor’s maximum I/O bandwidth from 80 Gbits/sec to 350 Tbits/sec (essentially unlimited I/O bandwidth).  This designer-defined approach allows SoC designers to more fully exploit advanced SoC silicon using tools that allow designers to quickly configure extremely powerful, tailored processors to specific tasks on the SoC. This presentation will illustrate the power and simplicity of an SoC development methodology that incorporates these design techniques.

Steven Leibson is the Technology Evangelist for Tensilica, Inc. He has formerly served as the Vice President of Content and Editor in Chief of the Microprocessor Report, Editor in Chief of EDN Magazine, and Founding Editor in Chief of Embedded Developers Journal magazine. He has written hundreds of articles that have appeared in several electronics industry trade magazines, and he has won many industry awards for his writing. While at MDR, Leibson developed and presented many microprocessor seminars, and he organized and served as MC for the Microprocessor and Embedded Processor Forums. He holds a BSEE Cum Laude from Case Western Reserve University and worked as a design engineer and engineering manager for leading-edge system-design companies including Hewlett-Packard and Cadnetix before becoming a journalist.

Charlie Cump, Vice President of Sales,  Elixent, Inc.

"Platform design for high volume and CE devices"

The challenges facing today's SoC developer are immense.  The end of the microprocessor's reign is being forecast, and yet at the same time the demise of custom hardware is, we're told, assured.  So how will we build tomorrow's solutions?  Many of today's solutions will be inappropriate in tomorrow's SoC world, and much that we have taken for granted will simply not work for tomorrow's convergence products. This presentation will focus on what is becoming the leading approach - using reconfigurable technology to implement programmable algorithm processing with the efficiency of hardware and the flexibility of software.  This approach complements the processors (configurable or otherwise) of today, and allows them to scale to address the toughest applications this decade will bring - whilst also directly addressing many of the direct challenges raised by deep sub micron economics. 

Louis Lippincott, Senior Engineering Manager, Consumer Electronics Group, Intel

"The MXP5800 Media Processor - Intel Media Processor"

Lou has worked in the area of digital video for the last twenty years, including several years at the David Sarnoff Research Center. Lou currently works in the Technology Office of Intel's Consumer Electronics Group. Before rejoining Intel in 1999, Lou worked as the Director of Hardware Engineering at Princeton Video Image, Inc. where he helped develop PVI's Emmy Award winning real-time video insertion technology, better known for the yellow first down line in football game broadcasts. Lou holds 20 US and foreign patents and has approximately 25 additional patents pending.

The need for performance on the order of about 100GOPs and the low-power restrictions of consumer electronic devices present several difficult processor architecture challenges. The typical strategies of faster and wider data paths simply do not lead to a workable solution. The MXP5800 architecture team had several key goals in mind as they developed the architecture. Firstly, we wanted an architecture that was well suited for easy implementation. We also wanted an architecture that could scale pre-silicon as well as post-silicon and we wanted an architecture that would be forgiving to last-minute changes in functionality. The MXP5800 architecture has the following characteristics: (1) Scalable, allowing for pre-silicon and post-silicon scaling. (2) Modular, allowing for easy silicon implementation. (3) Massively parallel, yielding very high performance and a high MIPs/mW ratio. (4) Optimized for a set of applications, yielding a high MOPs/mm2 ratio. As is true with all development projects, there were many tradeoffs that had to be made. We knowingly sacrificed ease of programmability for architecture efficiency. We also made the conscious decision to sacrifice some flexibility for architecture efficiency. We decided to address the ease of programmability issue with a rich set of programming and development tools.  We addressed the flexibility issue by making the architecture modular and scalable in nature. This strategy allows us to quickly turn out new devices that are specialized for their own intended applications.

David Fritz, Vice President of Business Development, ARC International

Mr. Fritz holds degrees in Mathematics and Computer Science from Manchester College and began his career at Texas Instruments and DSC Communications. He was the founder and President of Production Languages Corporation, a pioneer in configurable processor technology, where he was awarded a U.S. patent covering fundamental processes related to configurable processors. Production Languages Corporation was subsequently acquired by ZiLOG in 1999, and Mr. Fritz became Vice President of ZiLOG’s Advanced Cores R&D as well as Vice President of ZiLOG’s Development Systems Group. He currently serves as Vice President of Technical Marketing for ARC International.

CPUs and DSPs for SoC Platform Design Cont.

Dr. Thanh Tran, Senior Member Technical Staff,  Texas Instruments, Inc.

Dave Steer, Director of Segment Marketing, ARM, Inc.

"ARM's Data Engine Technology for Multimedia Applications”

Dave Steer is Director of Segment Marketing for ARM's US Operations. He is responsible for generating demand for ARM products and solutions among OEMs in all of ARM's target market segments. Since joining ARM in 1994, Dave has served in a variety of marketing, sales and engineering roles, contributing to the company's success in the storage and wireless markets and taking several technical leadership roles.

  4:15 pm - 5:15 pm

Panel: CPUs and DSPs for SoC Platform Design

Dave Bursky, Editor-at-Large, Electronic Design Magazine

Moderator

Dave Bursky, Editor-at-Large for Electronic Design magazine, joined Electronic Design in 1973, and has worked in various editorial positions, amassing more than 30 years of experience covering technology and product developments in the electronics industry.  Promoted to Editor-in-Chief in the fall of 1999 and to Editor-at-Large in early 2003, he has been responsible for defining the direction and content of Electronic Design. In addition to the editorial management responsibility, he has covered all aspects of Digital Semiconductor Technology, from processes to architectural definition, and from testing to circuit applications, for the magazine. He travels extensively around the U.S. as well as to Asia and Europe to interview company executives, and to attend trade shows and symposiums.  Additionally, Dave is one of several Electronic Design editors awarded the Jesse H. Neal award for Editorial Excellence. In 1988 he was described by an article in the San Jose Mercury News newspaper as one of the 100 most influential people in Silicon Valley. He has also taught digital logic technology at the former RCA Institute in New York City, and has been a guest lecturer at the Naval Post-Graduate School in Monterey, Calif.. Additionally, he has served on the program committees of numerous IEEE and commercial conferences, and has also moderated and organized technical presentation sessions at IEEE and commercial conferences. He has also authored six books on topics ranging from personal computers to semiconductor memories.  Prior to joining Electronic Design in 1973, he worked as a civilian electronics engineer at Fort Monmouth, N.J. on tactical computer systems and secure communication systems. Dave holds both Bachelor's and Master's degrees in Electrical Engineering from the City College of the City University of New York (1971 and 1973, respectively).  Dave lives in Silicon Valley and is married and has two children. In his spare time, he enjoys reading, stamp collecting, electronics (home-brew computing), and traveling.  

Arup Gupta, Chief Technology Officer, Consumer Electronics Group, Intel

Panelist

Arup Gupta is the CTO of the Consumer Electronics group at Intel. Arup joined Intel in late 2002. Prior to that he was the VP of Engineering at two startups Morphics Technology and Televersal Systems. Arup was the Engineering Director at Lucent Technologies leading Silicon and systems teams for complete reference design platforms in Consumer Wireless and Bluetooth till 2000. Arup spent over 14 years at AT&T/Lucent Bell Labs in various design and management positions. During his career he and his team have produced over 20 commercially successful DSPs, mixed signal and RF ICs. Arup's interest lies in Architecture for high performance signal processing and Reconfigurable computing. Arup has a MSEE from Washington State University and a BTech(Hons) from IIT Kharagpur, India in addition to several Executive management courses from Harvard University and Wharton School of Business. He has 3 patents awarded on DSP architectures and several patents pending. Arup is a Senior member of IEEE and a member of Sigma Xi.

Ralph Weir, Director of Technical Marketing, Elixent, Inc.

Panelist  

David Squires, Director of Marketing, DSP Division, Xilinx, Inc.

Panelist  

Panel: CPUs and DSPs for SoC Platform Design

Moderator: Dave Bursky, Editor-at-Large, Electronic Design Magazine

Panelists:

1. Steve Leibson, Technology Evangelist, Tensilica

2. Arup Gupta, Chief Technology Officer, Consumer Electronics Group, Intel

3. Dave Steer, Director of Segment Marketing, ARM Inc.

4. Dr. Thanh Tran, Senior Member Technical Staff,  Texas Instruments Inc

5. Ralph Weir, Director of Technical Marketing, Elixent

6. David Squires, Director of Marketing, DSP Division, Xilinx, Inc.

 Conference Exhibit & Reception Open

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