System-on-Chip (SoC) Seminar

In this two-day seminar the System-on-Chip (SoC) concept will be discussed from a system architecture viewpoint.  Related technologies, semiconductor vendor selection, performance issues, IP determination and selection, EDA tools, design and verification process, and other related subjects will be presented in depth from a practical, real-world business perspective. Industry and academic experts will present the latest approaches, technologies, and EDA challenges in a typical SoC design implementation.

This seminar will be conducted in a real-world engineering environment.  It allows seminar attendees to participate interactively in architectural brainstorming, design discussions, and trade-offs. It also addresses cost issues, tool challenges, availability of technologies and IPs, and much more.

In addition, a panel discussion allows other industry and academic professionals to further share insights and viewpoints with seminar participants at the conclusion of each day.

At this two-day seminar, attendees will learn:

1. Why SoC? Why not ASSP or ASIC?
   1. Cost analysis with practical, real-world example
   2. Performance discussion and analysis
2. System-level functional block diagram using a typical system such as router
3. Software requirements (system OS, required algorithms, etc.) and system software issues
4. Chip (proposed SoC) specifications with detailed power, performance, and functional requirements
:
1. Required technology (CMOS, etc.)
2. Performance
3. Required IPs such as CPU/s, DSP/s, etc.
4. I/O requirements
5. Internal architecture and interfaces
6. Power analysis and requirements
7. Packaging requirements
8. Cost (NRE, etc.)
9. And more ...
5. Semiconductor vendor selection. Which technology, IP, and design services? Issues such as Fab, cost, and other subjects will be covered as well as:
1. Overview of various semiconductor technologies
2. What to look for in selecting a semiconductor partner
3. Availability of technologies and IPs
4. Availability of I/Os (IP and cell)
5. FAB capacity and availability (commitment)
6. Partners for third-party EDA tools
7. Local support
6. Final SoC chip functionality and feature selection
7. SoC design, development, and verification 
   1. IP integration, hardware integration issues (on-chip bus interconnect, verification), software issues (availability of OS-based drivers such as Linux, WinCE, etc.)
   2. Verification strategies such as co-modeling functional simulation using component/module/IP modeling with Verilog, VHDL, or C. This includes discussion on why Verilog, VHDL, System Verilog, or C? Advantage or disadvantage of each?
   3. Emulation tools and modeling
   4. SoC power analysis and modeling, using the specified chip power requirement as a target
   5. SoC package selection using the specified chip pin requirement as a target
   6. SoC RTL source synthesis using synthesis and other industry-standard tools
   7. SoC Static Timing Analysis to check synthesized source timing. Discussion on timing and performance requirements
   8. SoC floor planning and trade-offs
   9. SoC placement routing and trade-offs
   10. SoC timing back annotation and verification using Standard Delay File (SDF)
   11. Manufacturing test strategies and methodologies that cover partial/full-scan, IDDQ testing, Built-In Self-Test (BIST), and others
   12. SoC sign-off requirements
8. Test board for SoC chip test and debug

Who Should Attend

This seminar is designed for all system designers, product development engineers, technical marketing and sales professionals, application engineers, engineering management, and business professionals who are interested in learning about SoC planning, design, implementation, and verification in a real-world approach.  

Dates/Time:  July 2007

Location: Irvine

Tuition:  TBD per person (includes all handouts and materials)

For schedule and location information, please contact: Sales@savantcompany.com

Cancellation and Refund Policy

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