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65/45nm Challenges for
Dick Tracy watch – Savant SoC Conference
As more and more phone
and PDA manufacturers integrate similar functions in their products, the
separating line between phones and PDAs is completely disappearing. The
resulting Smart Mobile Devices (SMDs) are becoming the standard products for
mass markets. Parallel to these developments, companies with little or no
history in the phone market are developing the first generation of practical
Dick Tracy watches that are bringing a new dimension to this technology
convergence. Today’s 3G WCDMA phones boast downloading speeds of 384kbps,
and many advanced, complex features are gradually becoming standard for
these phones (e.g., Integrated megapixel camera sensor, more than 10MB of
DRAM, 802.11b, Bluetooth, GPS, support for IPv4/IPv6 dual stack, hot swap
slot for SD Cards, MMC Cards, email and web browsing, and much more.)
Many PDA manufacturers
have already combined their products with phones, and today several CDMA-based
PDA phones or personal communicators are gaining market share in this
exploding dynamic segment. In addition to a larger LCD and a full qwerty
keyboard, these manufacturers provide many other capabilities, such as USB
2.0, more than 80MB of DRAM, support for multiple operating systems
(Windows, Symbian, etc.), and much more.
As in the PC industry,
SMDs’ overall system performance is driven by games, communication
protocols, business productivity tools, etc. However, there are two major
differences—people in their higher-end SMDs expect (1) a smaller/lighter
package and (2) a longer battery life!
High-level of
integration (System-on-Chip) in conjunction with advances in CMOS technology
has given the designer the needed tools to integrate more functionality into
a smaller die area (smaller/lighter
package). At the
same time, designers need to deal with tradeoffs associated with the
advances in CMOS scaling to meet the power-related issues (battery life). As
CMOS technologies scale down from 130nm to 90nm and lower, the main approach
for reducing power has been to scale down the supply voltage (VDD).
This voltage scaling is an effective technique for controlling the dynamic
power (CV2F) of ICs. However, as we lower the supply voltage (90nm and
lower), circuit speed degrades since switching-delay-time is proportional to
the load capacitance and the ratio of transistor threshold voltages to
transistor supply voltage (Vth/VDD).
For fast transistor switching, the Vth
must also be lowered in proportion to VDD,
which then increases the leakage current.
New power-aware design
methodologies and EDA tools are trying to address the leakage-current issue
in 90nm, 65nm, and beyond. Selected semiconductor manufacturers working on
65nm-process
technology are claiming that they are shrinking the equivalent 90nm designs
by 40% to 50%, boosting transistor performance by more than 35 percent, and
reducing the leakage current (i.e., the static power consumption) in the
idle transistors by a significant factor. These advances will allow
designers to integrate hundreds of millions of transistors that support both
analog and digital functions in the next generation System-on-Chip (SoC)
designs to meet demanding applications such as Smart Mobile Devices with TV,
biometric, and many other advanced features.
These challenging topics are some of the issues that will be addressed in
the Savant’s upcoming SoC Conference. More information is provided below or
at
www.savantcompany.com
Farhad Mafie
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Exclusive! New SoC Conference From Savant!
The 2nd
International System-on-Chip Conference, November 3 and 4, 2004, Bay
Area
http://www.savantcompany.com/SoC_Nov2004/SoC_Call.htm
Call
for Presenters:
The Savant SoC Conference Organizing Committee is pleased to announce a Call
for Presenters for The 2nd International System-on-Chip (SoC)
Conference, to be held in the Bay Area.
Track and session
presenters, keynote speakers, and panel members who can contribute their
professional expertise have a wonderful opportunity to share their
innovative SoC technology/SoC products at this event with a very focused and
targeted audience.
Deadline for proposals/abstracts: August 16, 2004.
(Please be sure to include a short bio and your photo along with your
proposal.)
Presenters and Keynote
speakers will be considered for leading-edge topics such as:
-
CMOS, Scaling, and the
Future
-
Interconnect-Centric
SoC Design
-
ASIC/SoC/Foundry for
90nm and Sub-90nm
-
SoC Design Challenges
-
Configurable CPUs and
DSPs for SoC Platform Design
-
SoC Design Using
Programmable ICs & Structured ASICs
-
System-on-Chip
Platform Design
-
EDA Tools for 90nm
and Post-90nm
-
New Ideas in Placement
and Floorplanning
-
New Opportunities in
High-level Synthesis
-
ASIC/SoC Design
Methodologies
-
IP Design, Modeling,
and Reuse
-
SoC Testing and
Verification
Panel moderators and
panel members will be considered for topics such as:
-
Configurable CPUs and
DSPs for SoC Platform Design
-
IP Design, Modeling,
and Reuse
-
EDA Tools for 90nm
and Post-90nm
-
SoC Testing and
Verification
Deadline for proposals/abstracts: August 16, 2004.
(Please be sure to include a short bio and your photo with your proposal.)
To
take advantage of this opportunity, please contact the Savant SoC Marketing
Team at
soc@savantcompany.com before August 16,
2004. Announcements to the public and general conference registration will
begin early September 2004.
We look forward to
talking with you and answering any questions you may have. Please share
this information with your colleagues!
For more
information, contact Savant Marketing:
Marketing@savantcompany.com
Please feel free to share this eNewsletter with other professionals! |
